Datasheet

AD9514
Rev. 0 | Page 4 of 28
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL Termination = 50 Ω to V
S
− 2 V
Output Rise Time, t
RP
60 100 ps 20% to 80%, measured differentially
Output Fall Time, t
FP
60 100 ps 80% to 20%, measured differentially
PROPAGATION DELAY, t
PECL
, CLK-TO-LVPECL OUT
Divide = 1 355 480 635 ps
Divide = 2 − 32 395 530 710 ps
Variation with Temperature 0.5 ps/°C
OUTPUT SKEW, LVPECL
OUT0 to OUT1 on Same Part, t
SKP
1
−50 0 +55 ps
Both LVPECL Outputs Across Multiple Parts, t
SKP_AB
2
125 ps
Same LVPECL Output Across Multiple Parts, t
SKP_AB
2
125 ps
LVDS Termination = 100 Ω differential, 3.5 mA
Output Rise Time, t
RL
200 350 ps 20% to 80%, measured differentially
Output Fall Time, t
FL
210 350 ps 80% to 20%, measured differentially
PROPAGATION DELAY, t
LVDS
, CLK-TO-LVDS OUT Optional delay off
Divide = 1 1.00 1.25 1.55 ns
Divide = 2 − 32 1.05 1.30 1.60 ns
Variation with Temperature 0.9 ps/°C
OUTPUT SKEW, LVDS Optional delay off
LVDS Output Across Multiple Parts, t
SKV_AB
2
230 ps
CMOS B outputs are inverted; termination = open
Output Rise Time, t
RC
650 865 ps 20% to 80%; C
LOAD
= 3 pF single-ended
Output Fall Time, t
FC
650 990 ps 80% to 20%; C
LOAD
= 3 pF single-ended
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS OUT Optional delay off
Divide = 1 1.10 1.45 1.75 ns
Divide = 2 − 32 1.15 1.50 1.80 ns
Variation with Temperature 1 ps/°C
OUTPUT SKEW, CMOS Optional delay off
CMOS Output Across Multiple Parts, t
SKC_AB
2
300 ps
LVPECL-TO-LVDS OUT
Output Delay, t
SKV_C
560 790 950 ps
LVPECL-TO-CMOS OUT
Output Delay, t
SKV_C
700 970 1150 ps
DELAY ADJUST (OUT2; LVDS and CMOS)
S0 = 1/3
Zero Scale Delay Time
3
0.34 ns
Zero Scale Variation with Temperature 0.20 ps/°C
Full Scale Time Delay
3
1.7 ns
Full Scale Variation with Temperature −0.38 ps/°C
S0 = 2/3
Zero Scale Delay Time
3
0.45 ns
Zero Scale Variation with Temperature 0.31 ps/°C
Full Scale Time Delay
3
5.9 ns
Full Scale Variation with Temperature −1.3 ps/°C