Datasheet

AD9514
Rev. 0 | Page 23 of 28
When the delay block is OFF (bypassed), it is also powered
down.
OUTPUTS
The AD9514 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0/OUT0B and OUT1/
OUT1B are LVPECL differential outputs. There are three
amounts of LVPECL differential voltage swing (V
OD
) that can be
selected (410 mV, 790 mV, and 960 mV) within the choices
available in
Table 11.
OUT2/OUT2B can be selected as either an LVDS differential
output or a pair of CMOS single-ended outputs. If selected as
CMOS, OUT2 is a noninverted, single-ended output, and
OUT2B is an inverted, single-ended output.
GND
3.3V
OUTB
OUT
05596-026
Figure 31. LVPECL Output Simplified Equivalent Circuit
OUTB
OUT
3
.5m
A
3
.5m
A
05596-027
Figure 32. LVDS Output Simplified Equivalent Circuit
05596-028
OUT2/
OUT2B
V
S
Figure 33. CMOS Equivalent Output Circuit
POWER SUPPLY
The AD9514 requires a 3.3 V ± 5% power supply for V
S
. The
tables in the
Specifications section give the performance
expected from the AD9514 with the power supply voltage
within this range. In no case should the absolute maximum
range of −0.3 V to +3.6 V, with respect to GND, be exceeded
on Pin VS.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9514 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as
possible to the part. The layout of the AD9514 evaluation board
(AD9514/PCB) is a good example.