Datasheet

AD9514
Rev. 0 | Page 11 of 28
TIMING DIAGRAMS
CLK
t
CMOS
t
CLK
t
LVDS
t
PECL
05596-002
Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode
05596-099
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
Figure 3. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
05596-003
Figure 4. LVDS Timing, Differential
SINGLE-ENDED
CMOS
3pF LOAD
80%
20%
t
RC
t
FC
05596-004
Figure 5. CMOS Timing, Single-Ended, 3 pF Load