Datasheet
AD9513
Rev. 0 | Page 9 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER
1
100 MHz output; incremental additive jitter
1
Delay FS = 1.8 ns Fine Adj. 00000 0.71 ps rms
Delay FS = 1.8 ns Fine Adj. 11111 1.2 ps rms
Delay FS = 6.0 ns Fine Adj. 00000 1.3 ps rms
Delay FS = 6.0 ns Fine Adj. 11111 2.7 ps rms
Delay FS = 11.6 ns Fine Adj. 00000 2.0 ps rms
Delay FS = 11.6 ns Fine Adj. 11111 2.8 ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
SYNCB
Logic High 2.7 V
Logic Low 0.40 V
Capacitance 2 pF
VREF
Output Voltage 0.62·V
S
0.76·V
S
V Minimum − maximum from 0 mA to 1 mA load
S0 TO S10
Levels
0 0.1·V
S
V
1/3 0.2·V
S
0.45·V
S
V
2/3 0.55·V
S
0.8·V
S
V
1 0.9·V
S
V
POWER
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER-ON SYNCHRONIZATION
1
35 ms See the Power-On SYNC section.
V
S
Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION 175 325 575 mW
All three outputs on. LVDS (divide = 2). No clock. Does not include
power dissipated in external resistors.
240 460 615 mW All three outputs on. CMOS (divide = 2); 62.5 MHz out (5 pF load).
320 605 840 mW All three outputs on. CMOS (divide = 2); 125 MHz out (5 pF load).
POWER DELTA
Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock.
LVDS Output 20 50 85 mW No clock.
CMOS Output (Static) 30 40 50 mW No clock.
CMOS Output (@ 62.5 MHz) 65 110 155 mW Single-ended. At 62.5 MHz out with 5 pF load.
CMOS Output (@ 125 MHz) 70 145 220 mW Single-ended. At 125 MHz out with 5 pF load.
Delay Block 30 45 65 mW Off to 1.8 ns fs, delay word = 60; output clocking at 62.5 MHz.
1
This is the rise time of the V
S
supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the V
S
to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs are not synchronized.