Datasheet

AD9513
Rev. 0 | Page 8 of 28
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS OUTPUT ADDITIVE TIME JITTER Calculated from SNR of ADC method
CLK= 400 MHz 300 fs rms
LVDS (OUT0) = 100 MHz
Divide Ratio = 4
LVDS (OUT1, OUT2) = 100 MHz Interferer
CLK = 400 MHz 300 fs rms
LVDS (OUT0) = 100 MHz
Divide Ratio = 4
LVDS (OUT1, OUT2) = 50 MHz Interferer
CLK = 400 MHz 305 fs rms
LVDS (OUT1) = 100 MHz
Divide Ratio = 4
LVDS (OUT0, OUT2) = 100 MHz Interferer
CLK = 400 MHz 310 fs rms
LVDS (OUT1) = 100 MHz
Divide Ratio = 4
LVDS (OUT0, OUT2) = 50 MHz Interferer
CLK = 400 MHz 310 fs rms
LVDS (OUT2) = 100 MHz
Divide Ratio = 4
LVDS (OUT0, OUT1) = 100 MHz Interferer
CLK = 400 MHz 315 fs rms
LVDS (OUT2) = 100 MHz
Divide Ratio = 4
LVDS (OUT0, OUT1) = 50 MHz Interferer
CLK = 400 MHz 345 fs rms
LVDS (OUT2) = 100 MHz
Divide Ratio = 4
CMOS (OUT0, OUT1) = 50 MHz Interferer
CMOS OUTPUT ADDITIVE TIME JITTER Calculated from SNR of ADC method
CLK = 400 MHz 300 fs rms
CMOS (OUT0) = 100 MHz
Divide Ratio = 4
LVDS (OUT2) = 100 MHz Interferer
CLK = 400 MHz 300 fs rms
CMOS (OUT0) = 100 MHz
Divide Ratio = 4
CMOS (OUT1, OUT2) = 50 MHz Interferer
CLK = 400 MHz 335 fs rms
CMOS (OUT1) = 100 MHz
Divide Ratio = 4
CMOS (OUT0, OUT2) = 50 MHz Interferer
CLK = 400 MHz 355 fs rms
CMOS (OUT2) = 100 MHz
Divide Ratio = 4
CMOS (OUT0, OUT1) = 50 MHz Interferer
CLK = 400 MHz 340 fs rms
CMOS (OUT2) = 100 MHz
Divide Ratio = 4
LVDS (OUT0, OUT1) = 50 MHz Interferer