Datasheet

AD9513
Rev. 0 | Page 4 of 28
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS Termination = 100 Ω differential
Output Rise Time, t
RL
200 350 ps 20% to 80%, measured differentially
Output Fall Time, t
FL
210 350 ps 80% to 20%, measured differentially
PROPAGATION DELAY, t
LVDS
, CLK-TO-LVDS OUT Delay off on OUT2
OUT0, OUT1, OUT2
Divide = 1 1.03 1.29 1.62 ns
Divide = 2 − 32 1.09 1.35 1.68 ns
Variation with Temperature 0.9 ps/°C
OUT2
Divide = 1 1.07 1.35 1.69 ns
Divide = 2 − 32 1.13 1.41 1.75 ns
Variation with Temperature 0.9 ps/°C
OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT2
OUT0 to OUT1 on Same Part, t
SKV
1
−135 −20 +125 ps
OUT0 to OUT2 on Same Part, t
SKV
1
−205 −65 +90 ps
All LVDS OUTs Across Multiple Parts, t
SKV_AB
2
375 ps
Same LVDS OUTs Across Multiple Parts, t
SKV_AB
2
300 ps
CMOS B outputs are inverted; termination = open
Output Rise Time, t
RC
650 865 ps 20% to 80%; C
LOAD
= 3 pF
Output Fall Time, t
FC
650 990 ps 80% to 20%; C
LOAD
= 3 pF
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS OUT Delay off on OUT2
OUT0, OUT1
Divide = 1 1.14 1.46 1.89 ns
Divide = 2 − 32 1.19 1.51 1.94 ns
Variation with Temperature 1 ps/°C
OUT2
Divide = 1 1.20 1.53 1.97 ns
Divide = 2 − 32 1.24 1.57 2.01 ns
Variation with Temperature 1 ps/°C
OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT2
All CMOS OUTs on Same Part, t
SKC
1
−230 +135 ps
All CMOS OUTs Across Multiple Parts, t
SKC_AB
2
415 ps
Same CMOS OUTs Across Multiple Parts, t
SKC_AB
2
330 ps
LVDS-TO-CMOS OUT Everything the same; different logic type
Output Skew, t
SKV_C
510 ps LVDS to CMOS on same part
DELAY ADJUST (OUT2; LVDS AND CMOS)
S0 = 1/3
Zero-Scale Delay Time
3
0.35 ns
Zero-Scale Variation with Temperature 0.20 ps/°C
Full-Scale Time Delay
3
1.8 ns
Full-Scale Variation with Temperature −0.38 ps/°C
S0 = 2/3
Zero-Scale Delay Time
3
0.48 ns
Zero-Scale Variation with Temperature 0.31 ps/°C
Full-Scale Time Delay
3
6.0 ns
Full-Scale Variation with Temperature −1.3 ps/°C