Datasheet

AD9513
Rev. 0 | Page 3 of 28
SPECIFICATIONS
Typical (typ) is given for V
S
= 3.3 V ± 5%; T
A
= 25°C, R
SET
= 4.12 kΩ, unless otherwise noted. Minimum (min) and maximum (max)
values are given over full V
S
and T
A
(−40°C to +85°C) variation.
CLOCK INPUT
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK INPUT (CLK)
Input Frequency 0 1.6 GHz
Input Sensitivity
1
150 mV p-p
Input Common-Mode Voltage, V
CM
1.5 1.6 1.7 V Self-biased; enables ac coupling
Input Common-Mode Range, V
CMR
1.3 1.8 V With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLKB ac-bypassed to RF ground
Input Resistance 4.0 4.8 5.6 kΩ Self-biased
Input Capacitance 2 pF
1
A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.
CLOCK OUTPUTS
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS CLOCK OUTPUT Termination = 100 Ω differential
Differential
Output Frequency 0 800 MHz
Differential Output Voltage (V
OD
) 250 350 450 mV
Delta V
OD
30 mV
Output Offset Voltage (V
OS
) 1.125 1.23 1.375 V
Delta V
OS
25 mV
Short-Circuit Current (I
SA
, I
SB
) 14 24 mA Output shorted to GND
CMOS CLOCK OUTPUT Single-ended measurements; termination open
Single-Ended Complementary output on (OUT1B)
Output Frequency 0 250 MHz With 5 pF load
Output Voltage High (V
OH
) V
S
− 0.1 V @ 1 mA load
Output Voltage Low (V
OL
) 0.1 V @ 1 mA load