Datasheet

AD9513
Rev. 0 | Page 19 of 28
Table 11. Output Delay Full Scale
S0 Delay
0 Bypass
1/3 1.8 ns
2/3 6.0 ns
1 11.6 ns
Table 12. Output Logic Configuration
S1 S2 OUT0 OUT1 OUT2
0 0 OFF LVDS OFF
1/3 0 CMOS CMOS OFF
2/3 0 LVDS LVDS OFF
1 0 LVDS CMOS OFF
0 1/3 CMOS CMOS CMOS
1/3 1/3 LVDS LVDS LVDS
2/3 1/3 LVDS LVDS CMOS
1 1/3 CMOS CMOS LVDS
0 2/3 OFF OFF OFF
1/3 2/3 OFF OFF LVDS
2/3 2/3 OFF OFF CMOS
1 2/3 OFF CMOS OFF
0 1 LVDS OFF CMOS
1/3 1 CMOS OFF LVDS
2/3 1 LVDS OFF LVDS
1 1 CMOS OFF CMOS
Table 13. OUT2 Delay or Phase
S3 S4
OUT2
Delay
(S0 ≠ 0)
OUT2
Phase
(S0 = 0)
0 0 0 0
1/3 0 1/16 1
2/3 0 1/8 2
1 0 3/16 3
0 1/3 1/4 4
1/3 1/3 5/16 5
2/3 1/3 3/8 6
1 1/3 7/16 7
0 2/3 1/2 8
1/3 2/3 9/16 9
2/3 2/3 5/8 10
1 2/3 11/16 11
0 1 3/4 12
1/3 1 13/16 13
2/3 1 7/8 14
1 1 15/16 15
Table 14. OUT2 Divide or OUT1 Phase
S5 S6
OUT2
Divide (Duty Cycle
1
)
(S2 ≠ 0)
OUT1
Phase
(S2 = 0)
0 0 1 0
1/3 0 2 (50%) 1
2/3 0 3 (33%) 2
1 0 4 (50%) 3
0 1/3 5 (40%) 4
1/3 1/3 6 (50%) 5
2/3 1/3 8 (50%) 6
1 1/3 9 (44%) 7
0 2/3 10 (50%) 8
1/3 2/3 12 (50%) 9
2/3 2/3 15 (47%) 10
1 2/3 16 (50%) 11
0 1 18 (50%) 12
1/3 1 24 (50%) 13
2/3 1 30 (50%) 14
1 1 32 (50%) 15
1
Duty cycle is the clock signal high time divided by the total period.
Table 15. OUT1 Divide or OUT2 Phase
S7 S8 OUT1
Divide (Duty Cycle
1
)
(S2 ≠ 1)
OUT2 Phase
(S2 = 1 and S0 ≠ 0)
0 0 1 0
1/3 0 2 (50%) 1
2/3 0 3 (33%) 2
1 0 4 (50%) 3
0 1/3 5 (40%) 4
1/3 1/3 6 (50%) 5
2/3 1/3 8 (50%) 6
1 1/3 9 (44%) 7
0 2/3 10 (50%) 8
1/3 2/3 12 (50%) 9
2/3 2/3 15 (47%) 10
1 2/3 16 (50%) 11
0 1 18 (50%) 12
1/3 1 24 (50%) 13
2/3 1 30 (50%) 14
1 1 32 (50%) 15
1
Duty cycle is the clock signal high time divided by the total period.