Datasheet

AD9513
Rev. 0 | Page 12 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1VS
2CLK
3CLKB
4VS
5SYNCB
6VREF
7S10
8S9
18 OUT2B
19 OUT2
20 VS
21 VS
22 OUT1B
23 OUT1
24 VS
17 VS
9
S8
10
S7
11
S6
13
S4
15
S2
1
4
S3
16
S1
12
S5
26
VS
27
OUT0B
28
OUT0
2
9
VS
30
VS
25
S0
TOP VIEW
(Not to Scale)
AD9513
31
GND
32
RSET
05595-005
Figure 5. 32-Lead LFCSP Pin Configuration
05595-006
1
32
8
9
25
24
16
17
THE EXPOSED PADDLE
IS AN ELECTRICAL AND
THERMAL CONNECTION
EXPOSED PAD
(BOTTOM VIEW)
GND
Figure 6. Exposed Paddle
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground.
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4 ,17 ,20, 21,
24, 26, 29, 30
VS Power Supply (3.3 V).
2 CLK Clock Input.
3 CLKB Complementary Clock Input.
5 SYNCB Used to Synchronize Outputs.
6 VREF Provides 2/3 V
S
for use as one of the four logic levels on S0 to S10.
7 to16, 25 S10 to S1, S0
Setup Select Pins. These are 4-state logic. The logic levels are V
S
, GND, 1/3 V
S
, and 2/3 V
S
. The
VREF pin provides 2/3 V
S
. Each pin is internally biased to 1/3 V
S
so that a pin requiring that logic
level should be left NC (no connection).
18 OUT2B Complementary LVDS/Inverted CMOS Output.
19 OUT2 LVDS/CMOS Output.
22 OUT1B Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block.
23 OUT1 LVDS/CMOS Output. OUT6 includes a delay block.
27 OUT0B Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block.
28 OUT0 LVDS/CMOS Output. OUT5 includes a delay block.
31 GND Ground. The exposed paddle on the back of the chip is also GND.
32 RSET Current Set Resistor to Ground. Nominal value = 4.12 kΩ.