Datasheet

AD9513
Rev. 0 | Page 10 of 28
TIMING DIAGRAMS
CLK
t
CLK
t
LVDS
t
CMOS
05595-002
Figure 2. CLK/CLKB to Clock Output Timing, DIV = 1 Mode
0
5595-065
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
Figure 3. LVDS Timing, Differential
0
5595-066
SINGLE-ENDED
CMOS
3pF LOAD
80%
20%
t
RC
t
FC
Figure 4. CMOS Timing, Single-Ended, 3 pF Load