Datasheet

AD9511
Rev. A | Page 52 of 60
Reg.
Addr.
(Hex)
Bit(s) Name Description
<3:0> Divider High Number of Clock Cycles Divider Output Stays High.
4A OUT0
(4C) (OUT1)
(4E) (OUT2)
(50) (OUT3)
(52) (OUT4)
<7:4> Divider Low Number of Clock Cycles Divider Output Stays Low.
4A OUT0
(4C) (OUT1)
(4E) (OUT2)
(50) (OUT3)
(52) (OUT4)
<3:0> Phase Offset Phase Offset (Default = 0000b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<4> Start Selects Start High or Start Low.
4B OUT0 (Default = 0b).
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<5> Force
Forces Individual Outputs to the State Specified in Start (Above).
This Function Requires That Nosync (Below) Also Be Set (Default = 0b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<6> Nosync Ignore Chip-Level Sync Signal (Default = 0b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<7> Bypass Divider Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
54 (55)
(56) (57)
<7:0> Not Used.
58 <0>
SYNC Detect
Enable
1 = Enable SYNC Detect (Default = 0b).
58 <1> SYNC Select
1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.
0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles.