Datasheet

AD9511
Rev. A | Page 50 of 60
Reg.
Addr.
(Hex)
Bit(s) Name Description
Fine Delay Adjust
34 <0>
Delay Control
OUT4
Delay Block Control Bit.
Bypasses Delay Block and Powers It Down (Default = 1b).
34 <7:1> Not Used.
35 <2:0>
Ramp Current
OUT4
The slowest ramp (200 µs) sets the longest full scale of approximately 10 ns.
<2> <1> <0> Ramp Current (μs)
0 0 0 200
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
35 <5:3>
Ramp Capacitor
OUT4
Selects the Number of Capacitors in Ramp Generation Circuit.
More Capacitors => Slower Ramp.
<5> <4> <3> Number of Capacitors
0 0 0 4 (Default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
35 <7:6> Not Used.
36 <0> Not Used.
36 <5:1>
Delay Fine Adjust
OUT4
Sets Delay Within Full Scale of the Ramp; There Are 32 Steps.
00000b => Zero Delay (Default).
11111b => Maximum Delay.
36 <7:6> Not Used.
37 (38) (39)
(3A) (3B)
(3C)
<7:0> Not Used.
Power-Down
LVPECL
OUT0
(OUT1)
(OUT2)
3D (3E) (3F) <1:0>
Mode <1> <0> Description Output
ON 0 0 Normal Operation ON
PD1 0 1 Test Only—Do Not Use OFF
PD2 1 0
Safe Power-Down
Partial Power-Down; Use If
Output Has Load Resistors
OFF
PD3 1 1
Total Power-Down
Use Only If Output Has No
Load Resistors
OFF