Datasheet

AD9511
Rev. A | Page 26 of 60
TYPICAL MODES OF OPERATION
PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY
CLOCK DISTRIBUTION
This is the most common operational mode for the AD9511.
An external oscillator (shown as VCO/VCXO) is phase locked
to a reference input frequency applied to REFIN. The loop filter
is usually a passive design. A VCO or a VCXO can be used. The
CLK2 input is connected internally to the feedback divider, N.
The CLK2 input provides the feedback path for the PLL. If the
VCO/VCXO frequency exceeds maximum frequency of the
output(s) being used, an appropriate divide ratio must be set in
the corresponding divider(s) in the
Distribution Section. Some
power can be saved by shutting off unused functions, as well as
by powering down any unused clock channels (see the
Register
Map and Description
section).
05286-010
R
N
PFD
STATUS
CHARGE
PUMP
LVPECL
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVDS/CMOS
DIVIDE
LVDS/CMOS
DIVIDE
Δ T
FUNCTION
V
REF
AD9511
PLL
REF
CLK1 CLK2
REFERENCE
INPUT
REFIN
LOOP
FILTER
VCXO,
VCO
CLOCK
OUTPUTS
SERIAL
PORT
Figure 30. PLL and Clock Distribution Mode
CLOCK DISTRIBUTION ONLY
It is possible to use only the distribution section whenever the
PLL section is not needed. Some power can be saved by
shutting the PLL block off, as well as by powering down any
unused clock channels (see the
Register Map Description
section).
In distribution mode, both the CLK1 and CLK2 inputs are
available for distribution to outputs via a low jitter multiplexer
(mux).
05286-011
R
N
PFD
STATUS
CHARGE
PUMP
LVPECL
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVDS/CMOS
DIVIDE
LVDS/CMOS
DIVIDE
Δ T
FUNCTION
V
REF
AD9511
PLL
REF
CLK1 CLK2
CLOCK
INPUT 1
REFIN
CLOCK
INPUT 2
CLOCK
OUTPUTS
SERIAL
PORT
Figure 31. Clock Distribution Mode