Datasheet

AD9511
Rev. A | Page 20 of 60
Table 13. Pin Function Descriptions
Pin No. Mnemonic Description
1 REFIN PLL Reference Input.
2 REFINB Complementary PLL Reference Input.
3, 6, 9, 18, 22,
23, 25, 28, 29,
32, 33, 36, 39,
40, 44, 48
VS Power Supply (3.3 V).
4 VCP
Charge Pump Power Supply. It should be greater than or equal to VS.
VCP can be set as high as 5.5 V for VCOs, requiring extended tuning range.
5 CP Charge Pump Output.
7 CLK2
Clock Input. Used to connect external VCO/VCXO to feedback divider, N. CLK2 also drives the
distribution section of the chip and may be used as a generic clock input when PLL is not used.
8 CLK2B Complementary Clock Input. Used in conjunction with CLK2.
10 CLK1 Clock Input. Drives distribution section of the chip.
11 CLK1B Complementary Clock Input. Used in conjunction with CLK1.
12 FUNCTION
Multipurpose Input. May be programmed as a reset (RESETB), sync (SYNCB), or power-down (PDB) pin.
This pin is internally pulled down by a 30 kΩ resistor. If this pin is left NC, the part is in reset by default.
To avoid this, connect this pin to V
S
with a 1 kΩ resistor.
13 STATUS Output Used to Monitor PLL Status and Sync Status.
14 SCLK Serial Data Clock.
15 SDIO Serial Data I/O.
16 SDO Serial Data Output.
17 CSB Serial Port Chip Select.
19, 24, 37,
38, 43, 46
GND Ground.
20 OUT2B Complementary LVPECL Output.
21 OUT2 LVPECL Output.
26 OUT1B Complementary LVPECL Output.
27 OUT1 LVPECL Output.
30 OUT4B Complementary LVDS/Inverted CMOS Output. OUT4 includes a delay block.
31 OUT4 LVDS/CMOS Output. OUT4 includes a delay block.
34 OUT3B Complementary LVDS/Inverted CMOS Output.
35 OUT3 LVDS/CMOS Output.
41 OUT0B Complementary LVPECL Output.
42 OUT0 LVPECL Output.
45 RSET Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
47 CPRSET Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 kΩ.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.