Datasheet

AD9511
Rev. A | Page 17 of 60
TIMING DIAGRAMS
05286-002
C
LK1
t
CMOS
t
CLK1
t
LVDS
t
PECL
Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode
05286-064
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
Figure 3. LVPECL Timing, Differential
05286-065
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
Figure 4. LVDS Timing, Differential
05286-066
SINGLE-ENDED
CMOS
3pF LOAD
80%
20%
t
RC
t
FC
Figure 5. CMOS Timing, Single-Ended, 3 pF Load