Datasheet

AD9511
Rev. A | Page 16 of 60
STATUS PIN
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS); there are other modes
in which the STATUS pin is not CMOS digital output. See
Figure 37.
Output Voltage High (V
OH
) 2.7 V
Output Voltage Low (V
OL
) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz
Applies when PLL mux is set to any divider or counter output,
or PFD up/down pulse. Also applies in analog lock detect mode.
Usually debug mode only. Beware that spurs may couple
to output when this pin is toggling.
ANALOG LOCK DETECT
Capacitance 3 pF
On-chip capacitance; used to calculate RC time
constant for analog lock detect readback. Use a pull-up resistor.
POWER
Table 11.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER-UP DEFAULT MODE POWER DISSIPATION 550 600 mW
Power-up default state; does not include power
dissipated in output load resistors. No clock.
POWER DISSIPATION 800 mW
All outputs on. Three LVPECL outputs @ 800 MHz,
two CMOS out @ 62 MHz (5 pF load). Does not include
power dissipated in external resistors.
850 mW
All outputs on. Three LVPECL outputs @ 800 MHz,
two CMOS out @ 125 MHz (5 pF load). Does not include
power dissipated in external resistors.
Full Sleep Power-Down 35 60 mW
Maximum sleep is entered by setting 0Ah<1:0> = 01b
and 58h<4> = 1b. This powers off the PLL BG and the
distribution BG references. Does not include power
dissipated in terminations.
Power-Down (PDB) 60 80 mW
Set FUNCTION pin for PDB operation by setting
58h<6:5> = 11b. Pull PDB low. Does not include
power dissipated in terminations.
POWER DELTA
CLK1, CLK2 Power-Down 10 15 25 mW
Divider, DIV 2 − 32 to Bypass 23 27 33 mW For each divider.
LVPECL Output Power-Down (PD2, PD3) 50 65 75 mW
For each output. Does not include dissipation
in termination (PD2 only).
LVDS Output Power-Down 80 92 110 mW For each output.
CMOS Output Power-Down (Static) 56 70 85 mW For each output. Static (no clock).
CMOS Output Power-Down (Dynamic) 115 150 190 mW
For each CMOS output, single-ended. Clocking at
62 MHz with 5 pF load.
CMOS Output Power-Down (Dynamic) 125 165 210 mW
For each CMOS output, single-ended. Clocking at
125 MHz with 5 pF load.
Delay Block Bypass 20 24 60 mW
Vs. delay block operation at 1 ns fs with maximum
delay; output clocking at 25 MHz.
PLL Section Power-Down 5 15 40 mW