Datasheet

AD9511
Rev. A | Page 15 of 60
SERIAL CONTROL PORT
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
CSB, SCLK (INPUTS)
CSB and SCLK have 30 kΩ
internal pull-down resistors
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current 10 nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 25 MHz
Pulse Width High, t
PWH
16 ns
Pulse Width Low, t
PWL
16 ns
SDIO to SCLK Setup, t
DS
2 ns
SCLK to SDIO Hold, t
DH
1 ns
SCLK to Valid SDIO and SDO, t
DV
6 ns
CSB to SCLK Setup and Hold, t
S
, t
H
2 ns
CSB Minimum Pulse Width High, t
PWH
3 ns
FUNCTION PIN
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS
The FUNCTION pin has a 30 kΩ internal pull-down resistor.
This pin should normally be held high. Do not leave NC.
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 110 µA
Logic 0 Current 1 µA
Capacitance 2 pF
RESET TIMING
Pulse Width Low 50 ns
SYNC TIMING
Pulse Width Low 1.5 High speed clock cycles
High speed clock is CLK1 or CLK2, whichever is
used for distribution.