Datasheet

AD9511
Rev. A | Page 14 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 400 MHz 555 fs rms
Calculated from SNR of ADC method;
F
C
= 100 MHz with A
IN
= 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
CMOS (OUT4) = 50 MHz (B Output On) Interferer(s)
DELAY BLOCK ADDITIVE TIME JITTER
1
Incremental additive jitter
100 MHz Output
Delay FS = 1 ns (1600 A, 1C) Fine Adj. 00000 0.61 ps
Delay FS = 1 ns (1600 A, 1C) Fine Adj. 11111 0.73 ps
Delay FS = 2 ns (800 A, 1C) Fine Adj. 00000 0.71 ps
Delay FS = 2 ns (800 A, 1C) Fine Adj. 11111 1.2 ps
Delay FS = 3 ns (800 A, 4C) Fine Adj. 00000 0.86 ps
Delay FS = 3 ns (800 A, 4C) Fine Adj. 11111 1.8 ps
Delay FS = 4 ns (400 A, 4C) Fine Adj. 00000 1.2 ps
Delay FS = 4 ns (400 A, 4C) Fine Adj. 11111 2.1 ps
Delay FS = 5 ns (200 A, 1C) Fine Adj. 00000 1.3 ps
Delay FS = 5 ns (200 A, 1C) Fine Adj. 11111 2.7 ps
Delay FS = 11 ns (200 A, 4C) Fine Adj. 00000 2.0 ps
Delay FS = 11 ns (200 A, 4C) Fine Adj. 00100 2.8 ps
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE NOISE AND SPURIOUS
Depends on VCO/VCXO selection. Measured at LVPECL
clock outputs; ABP = 6 ns; I
CP
= 5 mA; Ref = 30.72 MHz.
VCXO = 245.76 MHz,
F
PFD
= 1.2288 MHz; R = 25, N = 200
VCXO is Toyocom TCO-2112 245.76.
245.76 MHz Output Divide by 1.
Phase Noise @100 kHz Offset <−145 dBc/Hz Dominated by VCXO phase noise.
Spurious <−97 dBc
First and second harmonics of F
PFD
.
Below measurement floor.
61.44 MHz Output Divide by 4.
Phase Noise @100 kHz Offset <−155 dBc/Hz Dominated by VCXO phase noise.
Spurious <−97 dBc
First and second harmonics of F
PFD
.
Below measurement floor.