Datasheet

AD9510 Data Sheet
Rev. B | Page 52 of 56
Reg.
Addr.
(Hex) Bit(s) Name Description
[6] Nosync Ignore chip-level sync signal (default = 0b).
49
OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53
OUT5
55 OUT6
57 OUT7
[7]
Bypass divider
Bypass and power down divider logic; route clock directly to output (default = 0b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53
OUT5
55 OUT6
57 OUT7
58 [0] SYNC detect enable 1 = enable SYNC detect (default = 0b).
58
[1]
SYNC select
1 = raise flag if slow clocks are out-of-sync by 0.5 to 1 high speed clock cycles.
0 (default) = raise flag if slow clocks are out-of-sync by 1 to 1.5 high speed clock cycles.
58 [2] Soft SYNC
The Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that the polarity of
this bit is reversed. That is, a high level forces selected outputs into a known state, and a high > low
transition triggers a sync (default = 0b).
58 [3]
Dist ref
power-down
1 = power down the references for the distribution section (default = 0b).
58 [4] SYNC power-down 1 = power down the SYNC (default = 0b).
58 [6:5]
FUNCTION pin
select
[6] [5] Function
0 0 RESETB (default)
0 1 SYNCB
1 0 Test only, do not use
1 1 PDB
58 [7] Not used.
59 [7:0] Not used.
5A [0] Update registers
Writing a 1 to this bit updates all registers and transfers all serial control port register buffer contents to
the control registers on the next rising SCLK edge. This is a self-clearing bit; a 0 does not have to be
written to clear it.
5A
[7:1]
Not used.
End