Datasheet

Data Sheet AD9510
Rev. B | Page 51 of 56
Reg.
Addr.
(Hex) Bit(s) Name Description
[3:0] Divider high Number of clock cycles divider output stays high.
48
OUT0
4A OUT1
4C OUT2
4E OUT3
50 OUT4
52
OUT5
54 OUT6
56 OUT7
[7:4]
Divider low
Number of clock cycles divider output stays low.
48 OUT0
4A OUT1
4C OUT2
4E OUT3
50 OUT4
52
OUT5
54 OUT6
56 OUT7
[3:0] Phase offset Phase offset (default = 0000b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51
OUT4
53 OUT5
55 OUT6
57 OUT7
[4] Start Selects start high or start low (default = 0b).
49 OUT0
4B OUT1
4D OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7
[5] Force
Forces individual outputs to the state specified in start (see the previous section of this table). This
function requires that Nosync (see the next section of this table) also be set (default = 0b).
49 OUT0
4B OUT1
4D
OUT2
4F OUT3
51 OUT4
53 OUT5
55 OUT6
57 OUT7