Datasheet

Data Sheet AD9510
Rev. B | Page 49 of 56
Reg.
Addr.
(Hex) Bit(s) Name Description
[2:0] Ramp current
35
OUT5
The slowest ramp (200 µA) sets the longest full scale of approximately 10 ns.
39 OUT6
[2] [1] [0] Ramp Current (µA)
0 0 0 200
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
[5:3] Ramp capacitor Selects the number of capacitors in ramp generation circuit.
35 OUT5
More capacitors
→
slower ramp.
39
OUT6
[5] [4] [3] Number of Capacitors
0 0 0 4 (default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
[5:1] Delay fine adjust
36 OUT5 Sets delay within full scale of the ramp; there are 25 steps.
3A OUT6
00000
→
zero delay (default).
11000
→
maximum delay.
3C [1:0]
Power-down
LVPECL
3D
OUT0
3E OUT1
3F OUT2
OUT3
Mode [1] [0] Description Output
On 0 0 Normal operation. On
PD1 0 1 Test only—do not use. Off
PD2 1 0
Safe power-down. Partial power-down; use if output
has load resistors.
Off
PD3 1 1
Total power-down. Use only if output has no
load resistors.
Off
3C [3:2] Output level LVPECL
3D OUT0 Output single-ended voltage levels for LVPECL outputs.
3E
OUT1
3F OUT2
OUT3
[3] [2] Output Voltage (mV)
0 0 500
0 1 340
1 0 810 (default)
1 1 660