Datasheet

Data Sheet AD9510
Rev. B | Page 47 of 56
Reg.
Addr.
(Hex) Bit(s) Name Description
08 [5:2] PLL mux control
[5] [4] [3] [2] MUXOUT—Signal on STATUS Pin
0 0 0 0 Off (signal goes low) (default)
0 0 0 1 Digital lock detect (active high)
0 0 1 0 N divider output
0 0 1 1 Digital lock detect (active low)
0 1 0 0 R divider output
0 1 0 1 Analog lock detect (N channel, open-drain)
0 1 1 0 A counter output
0 1 1 1 Prescaler output (NCLK)
1 0 0 0 PFD up pulse
1
0
0
1
PFD down pulse
1 0 1 0 Loss of reference (active high)
1 0 1 1 Tristate
1 1 0 0 Analog lock detect (P channel, open-drain)
1 1 0 1 Loss of reference or loss of lock (inverse of DLD) (active high)
1 1 1 0 Loss of reference or loss of lock (inverse of DLD) (active low)
1 1 1 1 Loss of reference (active low)
MUXOUT is the PLL portion of the STATUS output MUX.
08 [6]
Phase frequency
detector (PFD)
polarity
0 = negative (default), 1 = positive.
08 [7] Not used.
09 [0] Reset all counters 0 = normal (default), 1 = reset R, A, and B counters.
09 [1] N-counter reset 0 = normal (default), 1 = reset A and B counters.
09 [2] R-counter reset 0 = normal (default), 1 = reset R counter.
09 [3] Not used.
09 [6:4]
Charge pump (CP)
current setting
[6] [5] [4] ICP (mA)
0 0 0 0.60
0
0
1
1.2
0 1 0 1.8
0 1 1 2.4
1 0 0 3.0
1 0 1 3.6
1 1 0 4.2
1 1 1 4.8
Default = 000b.
These currents assume: CPR
SET
= 5.1 kΩ.
Actual current can be calculated by: CP_LSB = 3.06/CPR
SET.
09 [7] Not used.
0A [1:0] PLL power-down 01 = Asynchronous power-down (default).
[1] [0] Mode
0
0
Normal operation
0 1 Asynchronous power-down
1 0 Normal operation
1 1 Synchronous power-down