Datasheet
AD9510 Data Sheet
Rev. B | Page 44 of 56
REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 24. AD9510 Register Map
Addr
(Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Def.
Value
(Hex) Notes
00
Serial
control port
configuration
SDO inactive
(bidirectional
mode)
LSB_
FIRST
Soft
reset
Long
instruction
Not used
10
01
Not used
02 Not used
03 Not used
PLL
PLL starts
in power-
down
04 A counter Not used 6-Bit A counter[5:0] 00
N divider
(A)
05
B counter
Not used
13-Bit B counter, Bits[12:8], MSB[4:0]
00
N divider
(B)
06 B counter 13-Bit B counter, Bits[7:0], LSB[7:0] 00
N divider
(B)
07 PLL 1 Not used
LOR
LOCK_DEL[6:5]
Not used
LOR
enable
Not used 00
08 PLL 2 Not used
PFD
polarity
PLL mux select[5:2] signal on STATUS pin CP mode[1:0] 00
09 PLL 3 Not used CP current[6:4]
Not
used
Reset R
counter
Reset N
counter
Reset All
counters
00
0A PLL 4 Not used
B
bypass
Not
used
Prescaler P[4:2] Power-down[1:0] 01
N divider
(P)
0B R divider Not used 14-Bit R divider, Bits[13:8], MSB[5:0] 00 R divider
0C R divider 14-Bit R divider, Bits[13:8], MSB[7:0] 00 R divider
0D PLL 5 Not used
Digital
lock
det.
enable
Digital
lock
det.
window
Not used
Antibacklash
pulse width[1:0]
00
0E33 Not used
Fine delay
adjust
Fine delays
bypassed
34
Delay
Bypass 5
Not used Bypass 01
Bypass
delay
35
Delay Full-
Scale 5
Not used Ramp capacitor[5:3] Ramp current [2:0] 00
Max. delay
full-scale
36
Delay Fine
Adjust 5
Not used
5-bit fine delay[5:1] (00000b to 11000b)
Must be
0
00
Min. delay
value
37 Not used 04
38
Delay
Bypass 6
Not used Bypass 01
Bypass
delay
39
Delay Full-
Scale 6
Not used Ramp capacitor[5:3] Ramp current[2:0] 00
Max. delay
full-scale
3A
Delay Fine
Adjust 6
Not used 5-bit fine delay[5:1] (00000b to 11000b)
Not
used
00
Min. delay
value
3B Not used 04
Outputs
3C LVPECL OUT0 Not used Output level[3:2] Power-down[1:0] 0A Off
3D LVPECL OUT1 Not used Output level[3:2] Power-down[1:0] 08 On