Datasheet

Data Sheet AD9510
Rev. B | Page 43 of 56
Figure 51. Serial Control Port Timing—Write
Table 23. Serial Control Port Timing
Parameter Description
t
DS
Setup time between data and rising edge of SCLK
t
DH
Hold time between data and rising edge of SCLK
t
CLK
Period of the clock
t
S
Setup time between CSB and SCLK
t
H
Hold time between CSB and SCLK
t
HI
Minimum period that SCLK must be in a logic high state
t
LO
Minimum period that SCLK must be in a logic low state
Figure 52. Use of CSB to Define Communications Cycle
05046-040
CSB
SCLK
SDIO
t
HI
t
LO
t
CLK
t
S
t
DS
t
DH
t
H
BI N BI N + 1
05046-067
CSB
CSB TOGGLE INDICATES
CYCLE COMPLETE
16 INSTRUCTION BITS + 8 DATA BITS 16 INSTRUCTION BITS + 8 DATA BITS
COMMUNICATION CYCLE 1 COMMUNICATION CYCLE 2
TIMING DIAGRAM FOR TWO SUCCESSIVE CUMMUNICATION CYCLES. NOTE THAT CSB MUST
BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.
t
PWH
SCLK
SDIO