Datasheet

AD9510 Data Sheet
Rev. B | Page 4 of 56
SPECIFICATIONS
Typical (typ) is given for V
S
= 3.3 V ± 5%, V
S
≤ VCP
S
≤ 5.5 V, T
A
= 25°C, R
SET
= 4.12 kΩ, CPR
SET
= 5.1 kΩ, unless otherwise noted.
Minimum (min) and maximum (max) values are given over full V
S
and T
A
(−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUTS (REFIN)
Input Frequency 0 250 MHz
Input Sensitivity
150
mV p-p
Self-Bias Voltage, REFIN 1.45 1.60 1.75 V Self-bias voltage of REFIN
1
Self-Bias Voltage, REFINB 1.40 1.50 1.60 V Self-bias voltage of REFINB
1
Input Resistance, REFIN 4.0 4.9 5.8 kΩ Self-biased
1
Input Resistance, REFINB 4.5 5.4 6.3 kΩ Self-biased
1
Input Capacitance 2 pF
PHASE FREQUENCY DETECTOR (PFD)
PFD Input Frequency 100 MHz Antibacklash pulse width, Register 0x0D[1:0] = 00b
PFD Input Frequency 100 MHz Antibacklash pulse width, Register 0x0D[1:0] = 01b
PFD Input Frequency 45 MHz Antibacklash pulse width, Register 0x0D[1:0] = 10b
Antibacklash Pulse Width 1.3 ns Register 0x0D[1:0] = 00b (this is the default setting)
Antibacklash Pulse Width 2.9 ns Register 0x0D[1:0] = 01b
Antibacklash Pulse Width 6.0 ns Register 0x0D[1:0] = 10b
CHARGE PUMP (CP)
I
CP
Sink/Source Programmable
High Value 4.8 mA With CPR
SET
= 5.1 kΩ
Low Value 0.60 mA
Absolute Accuracy
2.5
%
V
CP
= VCP
S
/2
CPR
SET
Range 2.7/10 kΩ
I
CP
Three-State Leakage 1 nA
Sink-and-Source Current Matching 2 % 0.5 < V
CP
< VCP
S
− 0.5 V
I
CP
vs. V
CP
1.5 % 0.5 < V
CP
< VCP
S
− 0.5 V
I
CP
vs. Temperature 2 % V
CP
= VCP
S
/2 V
RF CHARACTERISTICS (CLK2)
2
Input Frequency 1.6 GHz
Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS)
require a minimum divide-by-2 (see the Distribution
Section)
Input Sensitivity 150 mV p-p
Input Common-Mode Voltage, V
CM
1.5 1.6 1.7 V Self-biased, enables ac coupling
Input Common-Mode Range, V
CMR
1.3 1.8 V With 200 mV p-p signal applied
Input Sensitivity, Single-Ended 150 mV p-p
CLK2 ac-coupled, CLK2B capacitively bypassed to RF
ground
Input Resistance 4.0 4.8 5.6 kΩ Self-biased
Input Capacitance 2 pF
CLK2 VS. REFIN DELAY 500 ps Difference at PFD
PRESCALER (PART OF N DIVIDER) See the VCO/VCXO Feedback Divider—N ( P, A , B ) section
Prescaler Input Frequency
P = 2 DM (2/3) 600 MHz
P = 4 DM (4/5) 1000 MHz
P = 8 DM (8/9) 1600 MHz
P = 16 DM (16/17) 1600 MHz
P = 32 DM (32/33) 1600 MHz
CLK2 Input Frequency for PLL
300
MHz
A, B counter input frequency