Datasheet

AD9510 Data Sheet
Rev. B | Page 36 of 56
Divider Phase Offset
The phase of each output can be selected, depending on the
divide ratio chosen. This is selected by writing the appropriate
values to the registers which set the phase and start high/low bit
for each output. These are the odd numbered registers from
Register 0x49 to Register 0x57. Each divider has a 4-bit phase
offset [3:0] and a start high or low bit [4].
Following a sync pulse, the phase offset word determines how
many fast clock (CLK1 or CLK2) cycles to wait before initiating
a clock output edge. The Start H/L bit determines if the divider
output starts low or high. By giving each divider a different
phase offset, output-to-output delays can be set in increments of
the fast clock period, t
CLK
.
Figure 39 shows four dividers, each set for DIV = 4, 50% duty
cycle. By incrementing the phase offset from 0 to 3, each output
is offset from the initial edge by a multiple of t
CLK
.
Figure 39. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 3
For example:
CLK1 = 491.52 MHz
t
CLK1
= 1/491.52 = 2.0345 ns
For DIV = 4
Phase Offset 0 = 0 ns
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
Phase Offset 3 = 6.104 ns
The four outputs can also be described as:
OUT1 = 0°
OUT2 = 90°
OUT3 = 180°
OUT4 = 270°
Setting the phase offset to Phase = 4 results in the same relative
phase as the first channel, Phase = 0° or 360°.
In general, by combining the 4-bit phase offset and the Start
H/L bit, there are 32 possible phase offset states (see Table 19).
Table 19. Phase Offset—Start H/L Bit
Phase Offset
(Fast Clock
Rising Edges)
Address 0x49 to Address 0x57
Phase Offset[3:0] Start H/L[4]
0
0
0
1 1 0
2 2 0
3 3 0
4 4 0
5 5 0
6 6 0
7 7 0
8 8 0
9 9 0
10 10 0
11
11
0
12 12 0
13 13 0
14 14 0
15 15 0
16 0 1
17
1
1
18 2 1
19 3 1
20 4 1
21 5 1
22
6
1
23 7 1
24 8 1
25 9 1
26 10 1
27 11 1
28
12
1
29 13 1
30 14 1
31 15 1
The resolution of the phase offset is set by the fast clock period
(t
CLK
) at CLK1 or CLK2. As a result, every divide ratio does not
have 32 unique phase offsets available. For any divide ratio, the
number of unique phase offsets is numerically equal to the
divide ratio (see Table 19):
DIV = 4
Unique Phase Offsets Are Phase = 0, 1, 2, 3
DIV= 7
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6
DIV = 18
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 16, 17
05046-035
CLOCK INPUT
CLK
DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
START = 0,
PHASE = 0
START = 0,
PHASE = 1
START = 0,
PHASE = 2
START = 0,
PHASE = 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
t
CLK
t
CLK
2 × t
CLK
3 × t
CLK