Datasheet

Data Sheet AD9510
Rev. B | Page 27 of 56
Figure 33. Functional Block Diagram Showing Maximum Frequencies
05046-013
R DIVIDER
N DIVIDER
CHARGE
PUMP
PLL
SETTINGS
CLK2
STATUS
CLK2B
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
OUT7
OUT7B
LVDS/CMOS
/1, /2, /3... /31, /32
OUT6
OUT6B
LVDS/CMOS
/1, /2, /3... /31, /32
OUT0
OUT0B
LVPECL
/1, /2, /3... /31, /32
OUT1
OUT1B
LVPECL
/1, /2, /3... /31, /32
OUT2
OUT2B
LVPECL
/1, /2, /3... /31, /32
OUT3
OUT3B
LVPECL
/1, /2, /3... /31, /32
OUT4
OUT4B
LVDS/CMOS
/1, /2, /3... /31, /32
OUT5
OUT5B
LVDS/CMOS
/1, /2, /3... /31, /32
CLK1
CLK1B
REFIN
250MHz
REFINB
FUNCTION
SCLK
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
CP
CPRSET
DISTRIBUTION
REF
SYNCB,
RESETB,
PDB
RSET
AD9510
GNDVS VCP
PLL
REF
PHASE
FREQUENCY
DETECTOR
1.6GHz
1.6GHz
1.2GHz
LVPECL
250MHz
CMOS
800MHz
LVDS
∆T
∆T