Datasheet

Data Sheet AD9510
Rev. B | Page 25 of 56
TYPICAL MODES OF OPERATION
PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY
CLOCK DISTRIBUTION
This is the most common operational mode for the AD9510.
An external oscillator (shown as VCO/VCXO) is phase locked
to a reference input frequency applied to REFIN. The loop filter
is usually a passive design. A VCO or a VCXO can be used. The
CLK2 input is connected internally to the feedback divider, N.
The CLK2 input provides the feedback path for the PLL. If the
VCO/VCXO frequency exceeds maximum frequency of the
output or outputs being used, an appropriate divide ratio must
be set in the corresponding divider or dividers in the Distribution
Section. Save some power by shutting off unused functions and
by powering down any unused clock channels (see the Register
Map and Description section).
Figure 30. PLL and Clock Distribution Mode
CLOCK DISTRIBUTION ONLY
It is possible to use only the distribution section whenever the
PLL section is not needed. Save power by shutting off the PLL
block, and by powering down any unused clock channels (see
the Register Map and Description section).
In distribution mode, both the CLK1 and CLK2 inputs are available
for distribution to outputs via a low jitter multiplexer (mux).
Figure 31. Clock Distribution Mode
05046-010
R
N
PFD
STATUS
CHARGE
PUMP
LVDS/CMOS
DIVIDE
LVDS/CMOS
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVDS/CMOS
DIVIDE
LVDS/CMOS
DIVIDE
∆ T
∆ T
SERIAL
PORT
FUNCTION
V
REF
AD9510
PLL
REF
CLK1 CLK2
REFERENCE
INPUT
REFIN
LOOP
FILTER
VCXO,
VCO
CLOCK
OUTPUTS
05046-011
R
N
PFD
STATUS
CHARGE
PUMP
LVDS/CMOS
DIVIDE
LVDS/CMOS
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVPECL
DIVIDE
LVDS/CMOS
DIVIDE
LVDS/CMOS
DIVIDE
∆ T
∆ T
SERIAL
PORT
FUNCTION
V
REF
AD9510
PLL
REF
CLK1 CLK2
CLOCK
INPUT 1
REFIN
CLOCK
INPUT 2
CLOCK
OUTPUTS