Datasheet

AD9510 Data Sheet
Rev. B | Page 16 of 56
TIMING DIAGRAMS
Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode
Figure 3. LVPECL Timing, Differential
Figure 4. LVDS Timing, Differential
Figure 5. CMOS Timing, Single-Ended, 3 pF Load
05046-002
CLK1
t
CMOS
t
CLK1
t
LVDS
t
PECL
05046-064
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
05046-065
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
05046-066
SINGLE-ENDED
CMOS
3pF LOAD
80%
20%
t
RC
t
FC