Datasheet

AD9510 Data Sheet
Rev. B | Page 14 of 56
Parameter Min Typ Max Unit Test Conditions/Comments
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current
10
nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
)
25
MHz
Pulse Width High, t
PWH
16 ns
Pulse Width Low, t
PWL
16 ns
SDIO to SCLK Setup, t
DS
2 ns
SCLK to SDIO Hold, t
DH
1 ns
SCLK to Valid SDIO and SDO, t
DV
6 ns
CSB to SCLK Setup and Hold, t
S
, t
H
2 ns
CSB Minimum Pulse Width High, t
PWH
3 ns
FUNCTION PIN
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS
FUNCTION pin has 30 kΩ internal pull-down resistor;
normally, hold this pin high; do not leave unconnected
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 110 µA
Logic 0 Current
1
µA
Capacitance 2 pF
RESET TIMING
Pulse Width Low 50 ns
SYNC TIMING
Pulse Width Low 1.5 High speed clock cycles
High speed clock is CLK1 or CLK2, whichever is being used
for distribution
STATUS PIN
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS), there are other modes in
which the STATUS pin is not CMOS digital output; see Figure 37
Output Voltage High (V
OH
) 2.7 V
Output Voltage Low (V
OL
) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz
Applies when PLL mux is set to any divider or counter output, or PFD up/
down pulse; also applies in analog lock detect mode; usually debug mode
only; beware that spurs can couple to output when this pin is toggling
ANALOG LOCK DETECT
Capacitance 3 pF
On-chip capacitance, used to calculate RC time constant for analog lock
detect readback; use a pull-up resistor