Datasheet

Data Sheet AD9510
Rev. B | Page 13 of 56
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 400 MHz 555 fs rms
Calculated from SNR of ADC method,
f
C
= 100 MHz with A
IN
= 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
All Other CMOS = 50 MHz (B Output On) Interferer(s)
DELAY BLOCK ADDITIVE TIME JITTER
1
Incremental additive jitter
1
100 MHz Output
Delay FS = 1 ns (1600 μA, 1C) Fine Adjust 00000 0.61 ps
Delay FS = 1 ns (1600 μA, 1C) Fine Adjust 11000 0.73 ps
Delay FS = 2 ns (800 μA, 1C) Fine Adjust 00000 0.71 ps
Delay FS = 2 ns (800 μA, 1C) Fine Adjust 11000 1.2 ps
Delay FS = 3 ns (800 μA, 4C) Fine Adjust 00000 0.86 ps
Delay FS = 3 ns (800 μA, 4C) Fine Adjust 11000 1.8 ps
Delay FS = 5 ns (400 μA, 4C) Fine Adjust 00000 1.2 ps
Delay FS = 5 ns (400 μA, 4C) Fine Adjust 11000 2.1 ps
Delay FS = 6 ns (200 μA, 1C) Fine Adjust 00000 1.3 ps
Delay FS = 6 ns (200 μA, 1C) Fine Adjust 11000 2.7 ps
Delay FS = 9 ns (200 μA, 4C) Fine Adjust 00000
2.0
ps
Delay FS = 9 ns (200 μA, 4C) Fine Adjust 00111 2.8 ps
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, add the LVDS or CMOS output
jitter to this value using the root sum of the squares (RSS) method.
PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE NOISE AND SPURIOUS
Depends on VCO/VCXO selection; measured at LVPECL
clock outputs, ABP = 6 ns; I
CP
= 5 mA; Ref = 30.72 MHz
VCXO = 245.76 MHz, f
PFD
= 1.2288 MHz,
R = 25, N = 200
VCXO = Toyocom TCO-2112 245.76
245.76 MHz Output Divide by 1
Phase Noise at 100 kHz Offset <−145 dBc/Hz Dominated by VCXO phase noise
Spurious
<−97
dBc
First and second harmonics of f
PFD
; below measurement floor
61.44 MHz Output Divide by 4
Phase Noise at 100 kHz Offset <−155 dBc/Hz Dominated by VCXO phase noise
Spurious <−97 dBc First and second harmonics of f
PFD
; below measurement floor
SERIAL CONTROL PORT
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
CSB, SCLK (INPUTS)
Inputs have 30 kΩ internal pull-down
resistors
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF