Datasheet

Data Sheet AD9510
Rev. B | Page 11 of 56
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 622.08 MHz 40 fs rms Bandwidth = 12 kHz − 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT3) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz 55 fs rms Bandwidth = 12 kHz − 20 MHz (OC-3)
Any LVPECL (OUT0 to OUT3) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz 215 fs rms
Calculated from signal-to-noise ratio (SNR) of
ADC method, f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz 215 fs rms
Calculated from SNR of ADC method,
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 100 MHz Interferer(s)
All LVDS (OUT4 to OUT7) = 100 MHz
Interferer(s)
CLK1 = 400 MHz 222 fs rms
Calculated from SNR of ADC method,
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz Interferer(s)
All LVDS (OUT4 to OUT7) = 50 MHz Interferer(s)
CLK1 = 400 MHz 225 fs rms
Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
Interferer(s)
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs Off) Interferer(s)
CLK1 = 400 MHz 225 fs rms
Calculated from SNR of ADC method,
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
Interferer(s)
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs On) Interferer(s)
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 400 MHz 264 fs rms
Calculated from SNR of ADC method,
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
319
fs rms
Calculated from SNR of ADC method,
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4