Datasheet

AD9508 Data Sheet
Rev. B | Page 8 of 40
EXTERNAL RESISTOR VALUES FOR PIN STRAPPING MODE
Table 7.
Parameter Resistor Polarity Min Typ Max Unit Test Conditions/Comments
EXTERNAL RESISTORS
Using 10% tolerance resistor
Voltage Level 0 Pull down to ground 820 Ω
Voltage Level 1
Pull down to ground 1.8 kΩ
Voltage Level 2
Pull down to ground 3.9 kΩ
Voltage Level 3
Pull down to ground 8.2 kΩ
Voltage Level 4
Pull up to VDD 820 Ω
Voltage Level 5
Pull up to VDD 1.8 kΩ
Voltage Level 6
Pull up to VDD
3.9
kΩ
Voltage Level 7 Pull up to VDD 8.2 kΩ
CLOCK OUTPUT ADDITIVE PHASE NOISE
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 1474.56 MHz, OUTx = 1474.56 MHz Input slew rate > 1 V/ns
Divide Ratio = 1
At 10 Hz Offset
−88 dBc/Hz
At 100 Hz Offset
−100 dBc/Hz
At 1 kHz Offset
−109 dBc/Hz
At 10 kHz Offset
−116 dBc/Hz
At 100 kHz Offset
−135 dBc/Hz
At 1 MHz Offset
−144 dBc/Hz
At 10 MHz Offset
−148 dBc/Hz
At 100 MHz Offset
−149 dBc/Hz
CLK-TO-HSTL OR LVDS or CMOS ADDITIVE PHASE NOISE
CLK = 625 MHz, OUTx = 125 MHz
Input slew rate > 1 V/ns
Divide Ratio = 5
At 10 Hz Offset
−114
dBc/Hz
At 100 Hz Offset −125 dBc/Hz
At 1 kHz Offset
−133 dBc/Hz
At 10 kHz Offset
−141 dBc/Hz
At 100 kHz Offset
−159 dBc/Hz
At 1 MHz Offset
−162 dBc/Hz
At 10 MHz Offset
−163 dBc/Hz
At 20 MHz Offset
−163 dBc/Hz
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 491.52 MHz, OUTx = 491.52 MHz Input slew rate > 1 V/ns
Divide Ratio = 1
At 10 Hz Offset
−100 dBc/Hz
At 100 Hz Offset
−111 dBc/Hz
At 1 kHz Offset
−120 dBc/Hz
At 10 kHz Offset
−127
dBc/Hz
At 100 kHz Offset −146 dBc/Hz
At 1 MHz Offset
−153 dBc/Hz
At 10 MHz Offset
−153 dBc/Hz
At 20 MHz Offset
−153 dBc/Hz