Datasheet

Data Sheet AD9508
Rev. B | Page 7 of 40
Parameter Min Typ Max Unit Test Conditions/Comments
As Output
Output Voltage
Logic 1 VDD − 0.4 V 1 mA load current
Logic 0 0.4 V 1 mA load current
SDO
Output Voltage
Logic 1 VDD − 0.4 V 1 mA load current
Logic 0
0.4
V
1 mA load current
TIMING
SCLK
Clock Rate, 1/t
CLK
30
MHz
Pulse Width High, t
HIGH
4.6 ns
Pulse Width Low, t
LOW
3.5 ns
SDIO to SCLK Setup, t
DS
2.9 ns
SCLK to SDIO Hold, t
DH
0 ns
SCLK to Valid SDIO and SDO, t
DV
15 ns
EE
AA
to SCLK Setup (t
S
) CS
3.4 ns
AACS
EE
AA
to SCLK Hold (t
C
)
0 ns
AACS
EE
AA
Minimum Pulse Width High
3.4 ns
SERIAL PORT SPECIFICATIONS—I
2
C MODE
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
SDA, SCL (AS INPUT)
Input Voltage
Logic 1
VDD − 0.4 V
Logic 0
0.4 V
Input Current
−40
0
µA
For V
IN
= 10% to 90% DVDD3
Hysteresis of Schmitt Trigger Inputs 150 mV
SDA (AS OUTPUT)
Output Logic 0 Voltage
0.4 V I
O
= 3 mA
Output Fall Time from V
IH (MIN)
to V
IL (MAX)
250 ns 10 pF ≤ C
b
≤ 400 pF
TIMING
SCL Clock Rate
400 kHz
Bus-Free Time Between a Stop and Start
Condition, t
BUF
1.3 µs
Repeated Start Condition Setup Time, t
SU; STA
0.6 µs
Repeated Hold Time Start Condition, t
HD; STA
0.6 µs
After this period, the first clock pulse is
generated
Stop Condition Setup Time, t
SU; STO
0.6 µs
Low Period of the SCL Clock, t
LOW
1.3 µs
High Period of the SCL Clock, t
HIGH
0.6 µs
Data Setup Time, t
SU; DAT
100 ns
Data Hold Time, t
HD; DAT
0 0.9 µs