Datasheet

AD9508 Data Sheet
Rev. B | Page 4 of 40
CLOCK INPUTS AND OUTPUT DC SPECIFICATIONS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CLOCK INPUTS
Differential Mode
Input Frequency 0 1650 MHz Differential input
Input Sensitivity 360 2200 mV p-p As measured with a differential probe; jitter
performance improves with higher slew
rates (greater voltage swing)
Input Common-Mode Voltage V
ICM
0.95 1.05 1.15 V Input pins are internally self biased, which
enables ac coupling
Input Voltage Offset 30 mV
DC-Coupled Input Common-
Mode Range
V
CMR
0.58 1.67 V This is the allowable common-mode
voltage range when dc-coupled
Pulse Width
Low 303 ps
High 303 ps
Input Resistance (Differential) 5.0 7 9 kΩ
Input Capacitance C
IN
2 pF
Input Bias Current (Each Pin) 100 400 µA Full input swing
CMOS CLOCK MODE (SINGLE-ENDED)
Input Frequency 250 MHz
Input Voltage
High V
IH
VDD/2 − 0.15 V
Low V
IL
VDD/2 + 0.15 V
Input Current
High I
INH
1 µA
Low I
INL
−142
µA
Input Capacitance C
IN
2 pF
LVDS CLOCK OUTPUTS
Termination = 100 Ω differential (OUTx,
OUTx
)
Output Frequency 1650 MHz
Output Voltage Differential V
OD
247 375 454 mV V
OH
− V
OL
measurement across a differential
pair at the default amplitude setting with
output driver not toggling; see Figure 6 for
variation over frequency
Delta V
OD
ΔV
OD
50 mV This is the absolute value of the difference
between V
OD
when the normal output is high
vs. when the complementary output is high
Offset Voltage V
OS
1.125 1.18 1.375 V (V
OH
+ V
OL
)/2 across a differential pair
Delta V
OS
ΔV
OS
50 mV This is the absolute value of the difference
between V
OS
when the normal output is high
vs. when the complementary output is high
Short-Circuit Current I
S
A, I
S
B 13.6 24 mA Each pin (output shorted to GND)
LVDS Duty Cycle 45 55 % Up to 750 MHz input
39 61 % 750 MHz to1500 MHz input
50.1 % 1650 MHz input
HSTL CLOCK OUTPUTS 100 Ω across differential pair; default
amplitude setting
Output Frequency 1650 MHz
Differential Output Voltage V
O
859 925 978 mV V
OH
− V
OL
with output driver static
Common-Mode Output Voltage V
OCM
905 940 971 mV (V
OH
+ V
OL
)/2 with output driver static
HSTL Duty Cycle 45 55 % Up to 750 MHz input
40 60 % 750 MHz to 1500 MHz input
50.9 % 1650 MHz input