Datasheet

Data Sheet AD9508
Rev. B | Page 37 of 40
Address Bits Bit Name Description
[3:1] OUT2 Mode[2:0] These bits determine the OUT2 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0 Reserved 0b = default
0x26
7
EN_CMOS_2P
Setting this bit enables the OUT2P CMOS driver
0 = disables the OUT2P CMOS driver (default)
1 = enables OUT2P CMOS driver
[6:5]
CMOS_2P_PHASE[1:0]
These bits determine the phase of the OUT2P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
4 EN_CMOS_2N Setting this bit enables the OUT2N CMOS driver
0 = disables the OUT2N CMOS driver (default)
1 = enables OUT2N CMOS driver
[3:2] CMOS_2N_PHASE[1:0] These bits determine the phase of the OUT2N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
[1:0] Reserved 00b = default
OUT3 FUNCTIONS (REGISTER 0x27 TO REGISTER 0x2C)
Table 33. Divide Ratio and Phase
Address Bits Bit Name Description
0x27 [7:0] OUT3 Divide Ratio[7:0]
Channel 3 10-bit divider value, Bits[7:0] (LSB). Bits[9:8] (MSB) reside in Register 0x28
below. Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0]
= 1 is divided by 2 … [9:0] = 1023 is divided by 1024.
0x28
[7:2]
Reserved
0x00 = default
[1:0]
OUT3 Divide Ratio[9:8]
Channel 3 10-bit divider value, Bits[9:8] (MSB). Bits[7:0] (LSB) reside in Register 0x27
above. Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0]
= 1 is divided by 2 … [9:0] = 1023 is divided by 1024.
0x29
[7:0] OUT3 Phase[7:0]
Channel 3 11-bit phase offset value, Bits[7:0] (LSB). Bits[10:8] (MSB) reside in Register 0x2A
below. Phase Offset = Channel Phase Offset Bits[10:0] . For example, [10:0] = 1 is the
minimum phase offset of ½ the input clock period, [10:0] = 2 is a phase offset of one
input clock period.… [10:0] = 2047 is a phase offset 2047 times ½ the input clock period
0x2A
[7:3]
Reserved
0x00 = default
[2:0]
OUT3 Phase[10:8]
Channel 3 11-bit phase offset value, Bits[10:8] (MSB). Bits[7:0] (LSB) reside in Register 0x29
above. Phase Offset = Channel Phase Offset Bits[10:0] . For example, [10:0] = 1 is the
minimum phase offset of ½ the input clock period, [10:0] = 2 is a phase offset of one
input clock period.… [10:0] = 2047 is a phase offset 2047 times ½ the input clock period.