Datasheet

AD9508 Data Sheet
Rev. B | Page 36 of 40
Address Bits Bit Name Description
0x20
7 EN_CMOS_1P Setting this bit enables the OUT1P CMOS driver
0 = disables the OUT1P CMOS driver (default)
1 = enables the OUT1P CMOS driver
[6:5] CMOS_1P_PHASE[1:0] These bits determine the phase of the OUT1P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
[4] EN_CMOS_1N Setting this bit enables the OUT1N CMOS driver
0 = disables the OUT1N CMOS driver (default)
1 = enables the OUT1N CMOS driver
[3:2] CMOS_1N_PHASE[1:0] These bits determine the phase of the OUT1N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
[1:0] Reserved 00b = default
OUT2 FUNCTIONS (REGISTER 0x21 TO REGISTER 0x26)
Table 31. Divide Ratio and Phase
Address
Bits
Bit Name
Description
0x21 [7:0] OUT2 Divide Ratio[7:0]
Channel 2 10-bit divider value, Bits[7:0] (LSB). Bits[9:8] (MSB) reside in Register 0x22
below. Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0]
= 1 is divided by 2 … [9:0] = 1023 is divided by 1024.
0x22
[7:2] Reserved 0x00 = default
[1:0]
OUT2 Divide Ratio[9:8]
Channel 2 10-bit divider value, Bits[9:8] (MSB). Bits[7:0] (LSB) reside in Register 0x21
above. Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0]
= 1 is divided by 2 … [9:0] = 1023 is divided by 1024.
0x23
[7:0] OUT2 Phase[7:0]
Channel 2 11-bit phase offset value, Bits[7:0] (LSB). Bits[10:8] (MSB) reside in Register 0x24
below. Phase Offset = Channel Phase Offset Bits[10:0]. For example, [10:0] = 1 is the
minimum phase offset of ½ the input clock period, [10:0] = 2 is a phase offset of one
input clock period.… [10:0] = 2047 is a phase offset 2047 times ½ the input clock period.
0x24
[7:3]
Reserved
0x00 = default
[2:0]
OUT2 Phase[10:8]
Channel 2 11-bit phase offset value, Bits[10:8] (MSB). Bits[7:0] (LSB) reside in Register 0x23
above. Phase Offset = Channel Phase Offset Bits[10:0]. For example, [10:0] = 1 is the
minimum phase offset of ½ the input clock period, [10:0] = 2 is a phase offset of one
input clock period.… [10:0] = 2047 is a phase offset 2047 times ½ the input clock period.
Table 32. Output Driver, Power Down, and Sync
Address Bits Bit Name Description
0x25
7 PD_2 Channel 2 power-down
6 SYNCMASK2 Setting this bit masks OUT2 from the output sync function
0 = Channel 2 is synchronized during output sync (default)
1 = Channel 2 is excluded from an output sync
[5:4] OUT2 Driver Phase[1:0] These bits determine the phase of the OUT2 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low