Datasheet

AD9508 Data Sheet
Rev. B | Page 34 of 40
OUT0 FUNCTIONS (REGISTER 0x15 TO REGISTER 0x1A)
Table 27. Divide Ratio and Phase
Address Bits Bit Name Description
0x15
[7:0]
OUT0 Divide Ratio[7:0]
Channel 0 10-bit divider value, Bits[7:0] (LSB). Bits[9:8] (MSB) reside in Register 0x16
below. Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0]
= 1 is divided by 2 … [9:0] = 1023 is divided by 1024.
0x16
[7:2]
Reserved
0x00 = default
[1:0] OUT0 Divide Ratio[9:8]
Channel 0 10-bit divider value, Bits[9:8] (MSB). Bits[7:0] (LSB) reside in Register 0x15
above. Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0]
= 1 is divided by 2 … [9:0] = 1023 is divided by 1024.
0x17
[7:0] OUT0 Phase[7:0]
Channel 0 11-bit phase offset value, Bits[7:0] (LSB). Bits[10:8] (MSB) reside in Register 0x18
below. Phase Offset = Channel Phase Offset Bits[10:0]. For example, [10:0] = 1 is the
minimum phase offset of ½ the input clock period, [10:0] = 2 is a phase offset of one
input clock period.… [10:0] = 2047 is a phase offset 2047 times ½ the input clock period.
0x18
[7:3]
Reserved
0x00 = default
[2:0]
OUT0 Phase[10:8]
Channel 0 11-bit phase offset value, Bits[10:8] (MSB). Bits[7:0] (LSB) reside in Register 0x17
above. Phase Offset = Channel Phase Offset Bits[10:0]. For example, [10:0] = 1 is the
minimum phase offset of ½ the input clock period, [10:0] = 2 is a phase offset of one
input clock period.… [10:0] = 2047 is a phase offset 2047 times ½ the input clock period.
Table 28. Output Driver, Power Down, and Sync
Address Bits Bit Name Description
0x19
7 PD_0 Channel 0 power down
6
SYNCMASK0
Setting this bit masks Channel 0 from the output sync function
0 = Channel 0 is synchronized during output sync (default)
1 = Channel 0 is excluded from an output sync
[5:4]
OUT0 Driver Phase[1:0]
These bits determine the phase of the OUT0 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
[3:1] OUT0 Mode[2:0] These bits determine the OUT0 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0 Reserved 0b = default
0x1A
7 EN_CMOS_0P Setting this bit enables the OUT0P CMOS driver
0 = disables the OUT0P CMOS driver (default)
1 = enables the OUT0P CMOS driver
[6:5] CMOS_0P_PHASE[1:0] These bits determine the phase of the OUT0P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
4 EN_CMOS_0N Setting this bit enables the OUT0N CMOS driver
0 = disables the OUT0N CMOS driver (default)
1 = enables the OUT0N CMOS driver