Datasheet

AD9508 Data Sheet
Rev. B | Page 32 of 40
REGISTER MAP
Register addresses that are not listed in Table 23 are unused, and writing to those registers has no effect. The user should write the default
value to sections of registers marked reserved.
The abbreviation, R, in the optional (Opt) column in Table 23 means read only and NS means that the value does not change during a soft
reset. Note that the default column is represented by Def.
Table 23. Register Map
Reg
Addr
(Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def
Serial Control Port Configuration and Part Identification
0x00 NS SPI control SDO enable
LSB first/
increment
address
Soft reset Reserved Soft reset
LSB first/
increment
address
SDO enable 00
0x00 NS I²C control Reserved Soft reset Reserved Soft reset Reserved 00
0x0A R, NS Silicon rev Silicon Revision[7:0] 00
0x0B R, NS Reserved Reserved 00
0x0C R, NS Part ID Clock Part Family ID[7:0] 05
0x0D R,NS Part ID Clock Part Family ID[15:8] 00
Chip Level Functions
0x12 Reserved Reserved 02
0x13 Sleep Reserved Sleep Reserved 00
0x14 NS SYNC_BAR Reserved SYNC_BAR 01
OUT0 Functions
0x15
OUT0
Divide
Ratio[9:0]
OUT0 Divide Ratio[7:0] 00
0x16 Reserved OUT0 Divide Ratio[9:8] 00
0x17
OUT0
Phase[9:0]
OUT0 Phase[7:0] 00
0x18 Reserved OUT0 Phase[10:8] 00
0x19 OUT0 Driver PD_0 SYNCMASK0 OUT0 Driver Phase[1:0] OUT0 Mode[2:0] Reserved 14
0x1A OUT0 CMOS EN_CMOS_0P CMOS_0P_PHASE[1:0] EN_CMOS_0N CMOS_0N_PHASE[1:0] Reserved 00
OUT1 Functions
0x1B
OUT1
Divide
Ratio[9:0]
OUT1 Divide Ratio[7:0] 00
0x1C Reserved OUT1 Divide Ratio[9:8] 00
0x1D
OUT1
Phase[9:0]
OUT1 Phase[7:0] 00
0x1E Reserved OUT1 Phase[10:8] 00
0x1F OUT1 Driver PD_1 SYNCMASK1 OUT1 Driver Phase[1:0] OUT1 Mode[2:0] Reserved 14
0x20 OUT1 CMOS EN_CMOS_1P CMOS_1P_PHASE[1:0] EN_CMOS_1N CMOS_1N_PHASE[1:0] Reserved 00
OUT2 Functions
0x21
OUT2
Divide
Ratio[9:0]
OUT2 Divide Ratio[7:0] 00
0x22 Reserved OUT2 Divide Ratio[9:8] 00
0x23
OUT2
Phase[9:0]
OUT2 Phase [7:0] 00
0x24 Reserved OUT2 Phase[10:8] 00
0x25 OUT2 Driver PD_2 SYNCMASK2 OUT2 Driver Phase[1:0] OUT2 Mode[2:0] Reserved 14
0x26 OUT2 CMOS EN_CMOS_2P CMOS_2P_PHASE[1:0] EN_CMOS_2N CMOS_2N_PHASE[1:0] Reserved 00
OUT3 Functions
0x27
OUT3
Divide
Ratio[9:0]
OUT3 Divide Ratio[7:0] 00
0x28 Reserved OUT3 Divide Ratio[9:8] 00
0x29
OUT3
Phase[9:0]
OUT3 Phase[7:0]
00
0x2A
Reserved
OUT3 Phase[10:8]
00
0x2B OUT3 Driver PD_3 SYNCMASK3 OUT3 Driver Phase[1:0] OUT3 Mode[2:0] Reserved 14
0x2C OUT3 CMOS EN_CMOS_3P CMOS_3P_PHASE[1:0] EN_CMOS_3N CMOS_3N_PHASE[1:0] Reserved 00