Datasheet

Data Sheet AD9508
Rev. B | Page 31 of 40
Figure 58. Data Transfer Process (Master Read Mode, Two-Byte Transfer)
Data Transfer Format
Write byte format: The write byte protocol writes a register address to the RAM, starting from the specified RAM address.
S Slave
Address
AA
W
EE
A RAM Address
High Byte
A RAM Address
Low Byte
A RAM
Data 0
A RAM
Data 1
A RAM
Data 2
A P
Send byte format: The send byte protocol sets up the register address for subsequent reads.
S Slave Address AA
W
EE
A RAM Address High Byte A RAM Address Low Byte A P
Receive byte format: The receive byte protocol reads the data byte(s) from RAM, starting from the current address.
S Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 AA
A
EE P
Read byte format: This is the combined format of the send byte and the receive byte.
S Slave
Address
AA
W
EE
A RAM
Address
High Byte
A RAM
Address
Low Byte
A Sr Slave
Address
R A RAM
Data 0
A RAM
Data 1
A RAM
Data 2
AA
A
EE P
I²C Serial Port Timing
Figure 59. I²C Serial Port Timing
Table 22. I²C Timing Definitions
Parameter Description
f
SCL
Serial clock
t
BUF
Bus free time between stop and start conditions
t
HD; STA
Repeated hold time start condition
t
SU; STA
Repeated start condition setup time
t
SU; STO
Stop condition setup time
t
HD; DAT
Data hold time
t
SU; DAT
Date setup time
t
LOW
SCL clock low period
t
HIGH
SCL clock high period
t
R
Minimum/maximum receive SCL and SDA rise time
t
F
Minimum/maximum receive SCL and SDA fall time
t
SP
Pulse width of voltage spikes that must be suppressed by the input filter
1 2
8 9
1 2
3 TO 73 TO 7 8 9 10
ACK FROM
MASTER RECEIVER
NACK FROM
MASTER RECEIVER
SDA
SCL
S
P
11161-039
S Sr S
P
SDA
SCL
t
SP
t
HD; STA
t
SU; STA
t
SU; DAT
t
HD; DAT
t
HD; STA
t
SU; STO
t
BUF
t
R
t
F
t
R
t
F
t
HIGH
t
LOW
11161-038