Datasheet

Data Sheet AD9508
Rev. B | Page 29 of 40
Table 20. Serial Control Port Timing
Parameter Description
t
DS
Setup time between data and the rising edge of SCLK
t
DH
Hold time between data and the rising edge of SCLK
t
CLK
Period of the clock
t
S
Setup time between the AACS
EE
AA
falling edge and the SCLK rising edge (start of the communication cycle)
t
C
Setup time between the SCLK rising edge and AACS
EE
AA
rising edge (end of the communication cycle)
t
HIGH
Minimum period that SCLK should be in a logic high state
t
LOW
Minimum period that SCLK should be in a logic low state
t
DV
SCLK to valid SDIO and SDO (see Figure 51)
I
2
C SERIAL PORT OPERATION
The I
2
C interface has the advantage of requiring only two control
pins and is a de facto standard throughout the I
2
C industr y.
However, its disadvantage is the programming speed, which is
400 kbps maximum. The AD9508 I²C port design is based on
the I²C fast mode standard; therefore, it supports both the 100 kHz
standard mode and 400 kHz fast mode. Fast mode imposes a glitch
tolerance requirement on the control signals; that is, the input
receivers ignore pulses of less than 50 ns duration.
The AD9508 I²C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I²C bus system, the AD9508 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9508.
The AD9508 uses direct 16-bit memory addressing rather than
traditional 8-bit memory addressing.
The AD9508 allows up to four unique slave devices to occupy
the I
2
C bus. These slave devices are accessed via a 7-bit slave
address that is transmitted as part of an I
2
C packet. Only the
device that has a matching slave address responds to subsequent
I
2
C commands. Table 16 lists the supported device slave
addresses.
I
2
C Bus Characteristics
Table 21 provides a summary of the various I
2
C abbreviations
used in the protocol.
Table 21. I
2
C Bus Abbreviation Definitions
Abbreviation
Definition
S Start
Sr Repeated start
P Stop
ACK Acknowledge
NACK No acknowledge
EE
W
Write
R
Read
The transfer of data is shown in Figure 54. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
Figure 54. Valid Bit Transfer
Start/stop functionality is shown in Figure 55. The start condition
is characterized by a high-to-low transition on the SDA line while
SCL is high. The start condition is always generated by the master
to initialize a data transfer. The stop condition is characterized
by a low-to-high transition on the SDA line while SCL is high.
The stop condition is always generated by the master to terminate
a data transfer. Every byte on the SDA line must be eight bits long.
Each byte must be followed by an acknowledge bit; bytes are sent
MSB first.
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. The acknowledge bit is communicated
by pulling the SDA
line low during the ninth clock pulse after
each 8-bit data byte (see Figure 56).
The no acknowledge bit (
ANACKA) is the ninth bit attached to any
8-bit data byte. The receiving device (receiver) always generates
the no acknowledge bit to inform the transmitter that the byte
has not been received. The no acknowledge bit is communi-
cated by leaving the SDA line high during the ninth clock pulse
after each 8-bit data byte.
DAT
A LINE
S
TABLE;
D
ATA V
ALID
CHANGE
OF DATA
ALLOWED
SD
A
SCL
11161-034