Datasheet

Data Sheet AD9508
Rev. B | Page 27 of 40
Write
When the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9508
. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (one, two, or three bytes or streaming mode) depends
on the W0 and W1 bits in the instruction byte. When not
streaming,
AA
CS
EE
AA
can be deasserted after each sequence of eight
bits to stall the bus (except after the last byte, where it ends the
cycle). When the bus is stalled, the serial transfer resumes when
AA
CS
EE
AA
is asserted. Deasserting the
AA
CS
EE
AA
pin on a nonbyte boundary resets
the serial control port. Reserved or blank registers are not skipped
automatically during a write sequence. Therefore, the user must
know what bit pattern to write to the reserved registers to preserve
proper operation of the device. Generally, it does not matter what
data is written to blank registers, but it is customary to write 0s.
Read
The AD9508 supports the long instruction mode only. If the
instruction word indicates a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in
the instruction word. N is the number of data bytes read and
depends on the W0 and W1 bits of the instruction word. The
readback data is valid on the falling edge of SCLK. Blank registers
are not skipped during readback.
A readback operation takes data from either the serial control
port buffer registers or the active registers.
SPI Instruction Word (16 Bits)
The MSB of the 16-bit instruction word is R/AA
W
EE
AA
, which indicates
whether the instruction is a read or a write. The next two bits, W1
and W0, indicate the number of bytes in the transfer. The final 13
bits are the register address (A12 to A0), which indicates the
starting register address of the read/write operation (see
Table 19).
SPI MSB First and LSB First Transfers
The AD9508 instruction word and payload can be MSB first or
LSB first; the default is MSB first. The LSB first mode can be set by
writing a 1 to Register 0x00, Bit 6. Immediately after the LSB first
bit is set, subsequent serial control port operations are LSB first.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant payload byte. Subsequent
data bytes must follow, in order, from high address to low address.
In MSB first mode, the serial control port internal address genera-
tor decrements for each data byte of the multibyte transfer cycle.
When Register 0x00, Bit 6 = 1 (LSB first), the instruction and
data bytes must be written from LSB to MSB. Multibyte data
transfers in LSB first format start with an instruction byte that
includes the register address of the least significant payload byte,
followed by multiple data bytes. The serial control port internal
byte address generator increments for each byte of the multibyte
transfer cycle.
For multibyte MSB first (default) I/O operations, the serial control
port register address decrements from the specified starting address
toward Address 0x00. For multibyte LSB first I/O operations, the
serial control port register address increments from the starting
address toward Address 0x2C. Reserved addresses are not skipped
during multibyte I/O operations; therefore, the user writes the
default value to a reserved register and writes 0s to unmapped
registers. Note that it is more efficient to issue a new write
command than to write the default value to more than two
consecutive reserved (or unmapped) registers.
Table 18. Streaming Mode (No Addresses Skipped)
Write Mode Address Direction Stop Sequence
LSB First
Increment 0x00 … 0x2C
MSB First
Decrement 0x2C … 0x00
Table 19. Serial Control Port, 16-Bit Instruction Word, MSB First Bit Map
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/AAW
EE
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
CS
SCLK
DON'T CARE
SDIO A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DON'T CARE
DON'T CARE
DON'T CARE
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
11161-028