Datasheet

Data Sheet AD9508
Rev. B | Page 25 of 40
PIN STRAPPING TO PROGRAM ON POWER-UP
The PROG_SEL input when set to Logic 1 places the AD9508 in
pin strapping control mode without the need for SPI or I
2
C
operations. In this mode, Pin S0 through Pin S5 program the
desired internal divider value and output logic type for each
output or to set the output to a high-Z state.
The maximum divide value is limited to divide-by-16 and phase
offset delay control is not supported in this mode. LVDS and
HSTL logic types are supported in this mode. However, if HSTL
mode is set and the 100 Ω output termination is removed, the
output swings to 1.8 V CMOS logic levels. In this configura-
tion, the differential outputs of the channel selected become two
single-ended CMOS signals. Those outputs maintain a 180° phase
relationship and share the same channel divider value.
Programming individual outputs and the output logic type is
performed by hardwiring specific resistor values to each of the
S0 to S5 pins. The other side of the resistor is then biased to
ground or VDD, depending on the desired settings. The actual
settings are applied after an internal ADC scans each one of the
S0 to S5 pins. An ADC scan is initiated by either the internal
power-on reset when the device is powered up or by toggling
the
SYNC
pin. If changes are made after the internal power-on
reset, the
SYNC
pin must be toggled before any new changes are
accepted.
Table 15 depicts all the pin strapping selections available for
each output channel divider value and logic type. The resistors
listed in Table 15 must have 10% or better tolerance.
Note that if all outputs use an output divider value of one and
use either HSTL outputs or 1.8 V CMOS output levels, then the
S0 to S5 pins can be grounded to accomplish that particular
configuration instead of using the 820 Ω resistor.
Table 15. Selection Table for Pin Strapping Control
Programming
Pins
ADC Voltage Level (0 Through 7) vs. Resistor Value vs. Divide Value and Logic Type
0 = 820 Ω
Pulled to
GND
1 = 1.8 kΩ
Pulled to
GND
2 = 3.9 kΩ
Pulled to
GND
3 = 8.2 kΩ
Pulled to
GND
4 = 820 Ω
Pulled to
VDD
5 = 1.8 kΩ
Pulled to
VDD
6 = 3.9 kΩ
Pulled to
VDD
7 = 8.2 kΩ
Pulled to
VDD Description
S0 ÷1 ÷2 ÷3 ÷4 ÷5 ÷6 ÷8 ÷16 SO is assigned to the
Channel 0 divider ratio only
S1 ÷1 ÷2 ÷3 ÷4 ÷5 ÷6 ÷8 ÷16 S1 is assigned to the
Channel 1 divider ratio only
S2 ÷1 ÷2 ÷3 ÷4 ÷5 ÷6 ÷8 ÷16 S2 is assigned to the
Channel 2 divider ratio only
S3 ÷1 ÷2 ÷3 ÷4 ÷5 ÷6 ÷8 ÷16 S3 is assigned to the
Channel 3 divider ratio only
S4 HSTL/
HSTL
HSTL/
LVDS
HSTL/
high-Z
LVDS/
HSTL
LVDS/
LVDS
LVDS/
high-Z
High-Z/
HSTL
High Z/
high-Z
S4 is assigned to Channel 0
and Channel 1 to select their
output logic types
S5 HSTL/
HSTL
HSTL/
LVDS
HSTL/
high-Z
LVDS/
HSTL
LVDS/
LVDS
LVDS/
high-Z
High-Z/
HSTL
High-Z/
high-Z
S5 is assigned to Channel 2
and Channel 3 to select their
output logic types