Datasheet

AD9508 Data Sheet
Rev. B | Page 24 of 40
OUTPUT CLOCK SYNCHRONIZATION
On power up, the default output channel divider value is divide-
by-1 if SPI and I
2
C programming modes are used. Therefore,
there is no real requirement for synchronization after power up
unless a change in divider value or a phase offset value is
desired. A hard asynchronous output synchronization is
executed by briefly pulling the
SYNC
pin low. This forces the
outputs to be edge aligned regardless of their divide ratio after
the
SYNC
pin is released.
If the sync mask bit is set to a Logic 1 in any output channel,
those channels continue working uninterrupted while a sync
operation is being applied to other channels. Outputs are pulled
low while
SYNC
is low if they are not masked by the sync mask
bit. This only applies if outputs are functioning under normal
operation with its logic level set to 11 or toggle mode.
POWER SUPPLY
The AD9508 is designed to work off a 3.3 V + 5% power supply
down to a 2.5 V − 5% power supply. Best practice recommends
bypassing the power supply on the printed circuit board (PCB)
with adequate capacitance (>10 µF) and bypassing all power pins
with adequate capacitance (0.1 µF) as close to the part as possible.
The layout of the AD9508 evaluation board (AD9508/PCBZ),
available at www.analog.com, provides a good layout example
for this device.
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
Exposed Metal Paddle
The exposed metal paddle on the AD9508 package is an
electrical connection, as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (VSS). The AD9508 dissipates heat through
its exposed paddle. The PCB acts as a heat sink for the AD9508.
The PCB attachment must provide a good thermal path to a
larger heat dissipation area, such as the ground plane on the
PCB. This requires a grid of vias from the top layer down to the
ground plane. See Figure 47 for an example.
Figure 47. PCB Land Example for Attaching Exposed Paddle
Refer to the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), for more information about mounting devices with
an exposed paddle.
VIAS TO GND PLANE
11161-145