Datasheet

Data Sheet AD9508
Rev. B | Page 21 of 40
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
Figure 41. Detailed Block Diagram
The AD9508 accepts either a differential input clock applied to
the CLK and
A
CLK
E
A
pins or a single-ended 1.8 V CMOS clock
applied to the CLK pin. The input clock signal is sent to the clock
distribution section, which has programmable dividers and
phase offset adjustment. The clock distribution section operates
at speeds of up to 1650 MHz.
The divider range under SPI or I
2
C control ranges from 1 to
divide-by-1024 and the phase offset adjustment is equipped with
11 bits of resolution. However, in pin programming mode, the
divider range is limited to a maximum divide-by-16 and there is
no phase offset adjustment available.
The outputs can be configured to as many as four LVDS/HSTL
differential outputs or as many as eight 1.8 V CMOS single-
ended outputs. In addition, the output current for the different
outputs is adjustable for output drive strength.
The device can be powered with either a 3.3 V or 2.5 V external
supply; however, the internal supply on the chip runs off an
internal 1.8 V LDO, delivering high performance with minimal
power consumption.
PROGRAMMING MODE SELECTION
The AD9508 supports both SPI and I²C protocols, and a pin
strapping option to program the device. The active interface
depends on the logic state of the PROG_SEL pin. See Table 13
for programming mode selections. See the Serial Control Port
and Pin Strapping to Program on Power-Up sections for more
detailed information.
Table 13. SPI/I²C/Pin Serial Port Setup
PROG_SEL
SPI/I²C/Pin
Float SPI
Logic 0
I²C
Logic 1 Pin programming control
CLOCK INPUT
The IN_SEL pin controls the desired input clock configuration.
When the IN_SEL pin is set for single-ended operation, the
device expects 1.8 V, 2.5 V, or 3.3 V CMOS-compatible logic
levels on the CLK input pin. Bypass the unused
A
CLK
E
A
pin to
ground with a 0.1 μF capacitor.
When the IN_SEL pin is set for differential input clock mode,
the inputs of the AD9508 are internally self biased. The internal
DIGITAL LOGIC
AND
REGISTERS
SPI
INTERFACE
I
2
C
INTERFACE
10-BIT
DIVIDER
SCL
SDA
CLK
SPI/I
2
C/PIN_
PROG
COARSE
A/D
PIN PROGRAM
READ CONTROL
SYNC
LVDS/HSTL/CMOS
OUTPUTS
LDO
SUB LDO
SUB LDO
VDD
RESET
LDO
REVISION ID
11-BIT
ΔΦ
11-BIT
ΔΦ
11-BIT
ΔΦ
11-BIT
ΔΦ
10-BIT
DIVIDER
10-BIT
DIVIDER
10-BIT
DIVIDER
CLK
IN_SEL
PROG_SEL
SCLK/SCL/S0
SDIO/SDA/S1
SDO/S3
S4
S5
CS/S2
EXT_CAP0
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
EXT_CAP1
VDD
11161-139
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