Datasheet

AD9508 Data Sheet
Rev. B | Page 16 of 40
Figure 21. HSTL Differential Output Swing vs. Power Supply Voltage
Figure 22. HSTL Propagation Delay vs. Input Differential Voltage
Figure 23. HSTL Propagation Delay vs. Input Common-Mode Voltage
Figure 24. HSTL Output Duty Cycle vs. Output Frequency
Figure 25. Additive Broadband Jitter vs. Input Slew Rate, LVDS, HSTL
(Calculated from SNR of ADC Method)
Figure 26. Absolute Phase Noise in HSTL Mode with Clock Input at
622.08 MHz and Outputs = 622.08 MHz, 311.04 MHz, 155.52 MHz
2.0
POWER SUPPLY (V)
2.3 2.5
3.1
2.92.7
3.3
3.5
DIFFERENTIAL OUTPUT SWING (mV p-p)
1.9
1.8
1.7
1.6
1.5
11161-021
11161-022
2.0
2.1
2.2
2.3
2.4
1.8
1.7
2.01.6 1.81.4
1.21.00.8
0.60.40.2
1.9
PROPAGATION DELAY (ns)
INPUT DIFFERENTIA
L (V p-p)
COMMON-MODE VOLTAGE (mV)
PROPAGATION DELAY (ns)
2.0
1.8
1.6
1.4
2.6
2.4
2.2
300
500
700
900
1100
1300 1500
11161-023
55
FREQUENCY (MHz)
4002000 600 800 1000 1200 1400 1600
DUTY CYCLE (%)
60
50
45
40
11161-024
DIVIDER 1
DIVIDER 2 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 800MHz)
DIVIDER 3 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 500MHz)
80
90
100
110
120
130
140
150
0 2 4 6 8 10
JITTER (fs rms)
SLEW RATE (V/ns)
11161-227
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
10 100 1k 10k 100k 10M 100M1M
PHASE NOISE
(dBc/Hz)
FREQUENCY OFFSET (Hz)
HSTL 155.52MHz
HSTL 311.04MHz
HSTL 622.08MHz
11161-228