Datasheet

AD9484
Rev. A | Page 5 of 24
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
MIN
= −40°C, T
MAX
= +85°C, f
IN
= −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3.
Parameter
1
Temp Min Typ Max Unit
CLOCK INPUTS
Logic Compliance Full CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage
High Level Input (V
IH
) Full 0.2 1.8 V p-p
Low Level Input (V
IL
) Full −1.8 −0.2 V p-p
High Level Input Current (I
IH
) Full −10 +10 μA
Low Level Input Current (I
IL
) Full −10 +10 μA
Input Resistance (Differential) Full 8 10 12 kΩ
Input Capacitance Full 4 pF
LOGIC INPUTS
Logic 1 Voltage Full 0.8 × DRVDD V
Logic 0 Voltage Full 0.2 × DRVDD V
Logic 1 Input Current (SDIO, CSB) Full 0 μA
Logic 0 Input Current (SDIO, CSB) Full −60 μA
Logic 1 Input Current (SCLK, PDWN) Full 50 μA
Logic 0 Input Current (SCLK, PDWN) Full 0 μA
Input Capacitance Full 4 pF
LOGIC OUTPUTS
2
V
OD
Differential Output Voltage Full 247 454 mV
V
OS
Output Offset Voltage Full 1.125 1.375 V
Output Coding
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
LVDS R
TERMINATION
= 100 Ω.