Datasheet

AD9484
Rev. A | Page 19 of 24
Table 10. Serial Timing Definitions
Parameter Minimum (ns) Description
t
DS
5 Setup time between the data and the rising edge of SCLK
t
DH
2 Hold time between the data and the rising edge of SCLK
t
CLK
40 Period of the clock
t
S
5 Setup time between CSB and SCLK
t
H
2 Hold time between CSB and SCLK
t
HIGH
16 Minimum period that SCLK should be in a logic high state
t
LOW
16 Minimum period that SCLK should be in a logic low state
t
EN_SDIO
1
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 39)
t
DIS_SDIO
5
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 39)
Table 11. Output Data Format
Input (V) Condition (V) Offset Binary Output Mode, D7± to D0± Twos Complement Mode, D7± to D0± OR±
VIN+ − VIN− < −0.75 − 0.5 LSB 0000 0000 1000 0000 1
VIN+ − VIN− = −0.75 0000 0000 1000 0000 0
VIN+ − VIN− = 0 1000 0000 0000 0000 0
VIN+ − VIN− = 0.75 1111 1111 0111 1111 0
VIN+ − VIN− > 0.75 + 0.5 LSB 1111 1111 0111 1111 1