Datasheet

AD9481
Rev. 0 | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.
Table 4.
AD9481-250
Parameter Temp Test Level Min Typ Max Unit
CLOCK
Maximum Conversion Rate Full VI 250 MSPS
Minimum Conversion Rate Full IV 20 MSPS
Clock Pulse-Width High (t
EH
) Full IV 1.2 2 ns
Clock Pulse-Width Low (t
EL
) Full IV 1.2 2 ns
DS Input Setup Time (t
SDS
) Full IV 0.5 ns
DS Input Hold Time (t
HDS
) Full IV 0.5 ns
OUTPUT PARAMETERS
1
Valid Time (t
V
)
2
Full VI 2.5 ns
Propagation Delay (t
PD
) Full VI 4 5.4 ns
Rise Time (t
R
) 10% to 90% Full V 670 ps
Fall Time (t
F
) 10% to 90% Full V 360 ps
DCO Propagation Delay (t
CPD
)
3
Full VI 2.5 3.9 5.3 ns
Data-to-DCO Skew (t
PD
− t
CPD
)
4
Full VI −0.5 +0.5 ns
A Port Data to DCO− Rising (t
SKA
)
5
Full IV 4 ns
B Port Data to DCO+ Rising (t
SKB
) Full IV 4 ns
Pipeline Latency (A, B) Full IV 8 Cycles
APERTURE
Aperture Delay (t
A
) 25°C V 1.5 ns
Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms
OUT-OF-RANGE RECOVERY TIME 25°C V 1 Cycle
1
C
LOAD
equals 5 pF maximum for all output switching specifications.
2
Valid time is approximately equal to minimum t
PD
.
3
T
CPD
equals clock rising edge to DCO (+ or −) rising edge delay.
4
Data changing to (DCO+ or DCO−) rising edge delay.
5
T
SKA
, T
SKB
are both clock rate dependent delays equal to T
CYCLE
− (Data to DCO skew).