Datasheet

AD9481
Rev. 0 | Page 24 of 28
PCB SCHEMATICS
NOTE: TWO 40 PIN OUTPUT CONNECTOR IMPLEMENTED AS ONE 80 PIN CONNECTOR
P1
P10
P11P12 P13P14 P15P16 P17P18 P19
P2 P20
P21P22 P23P24 P25P26 P27P28 P29
P3
P30
P31P32 P33P34 P35P36 P37P38 P39
P4 P40
P5P6 P7P8 P9
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
P3
GND
GND DR– GND DA7X DA6X DA5X DA4X DA3X DA2X DA1X DA0X
OUTPUT
CONNECTOR
RPAK_4
CLOCK
D0 D1 D2 D3 D4 D5 D6 D7 GND OUT_EN
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC
9
10 12 13 14 15
2 3 4 5 6 7 8 1
16 11
DA7X DA6X DA5X DA4X DA3X DA2X DA1X DA0X
VDL
GND
R39 X R38 X
VDLGND
GND
CLKLAT–
11
2 3 4 5 6 7 8 9
10
1
19 18 17 16 15 14 13 12 20
U7
74LVT574
2 3 4 1
8 7 6 5
U6
2 3 4 1
8 7 6 5
U5
DA0 DA1 DA2 DA3 DA7 DA5 DA4 DA6
100Ω
RP2
100Ω
RPAK_4
P1
P10
P11P12 P13P14 P15P16 P17P18 P19
P2 P20
P21P22 P23P24 P25P26 P27P28 P29
P3
P30
P31P32 P33P34 P35P36 P37P38 P39
P4 P40
P5P6 P7P8 P9
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
P23
GND
GND DR+ GND DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X
OUTPUT
CONNECTOR
RPAK_4
CLOCK
D0 D1 D2 D3 D4 D5 D6 D7 GND OUT_EN
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC
9
10 12 13 14 15
2 3 4 5 6 7 8 1
16 11
DB0X DB1X DB2X DB3X DB4X DB5X DB6X DB7X
VDL
GND
R41 X R40 X
VDLGND
GND
CLKLAT+
11
2 3 4 5 6 7 8 9
10
1
19 18 17 16 15 14 13 12 20
U4
74LVT574
2 3 4 1
8 7 6 5
U8
2 3 4 1
8 7 6 5
U3
DB7 DB6 DB5 DB4 DB0 DB2 DB3 DB1
100Ω
RP1
100Ω
RPAK_4
E72VCTRL E7VDL E12DRVDD E4AVDD E70AVDD E71DRVDD
X = NOT NORMALLY POPULATED XX = NOT POPULATED, USER SELECTED
AGND
AVDD
CLK+
CLK–
D0A D0B D1A D1B D2A D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
D7A
D7B
DCO+
DCO–
DRGND
DRVDD
DS+ DS–
PWDN
S1
S3
SENSE
VIN+ VIN– VREF
DRVDD
DRGNDAVDD
AGND AVDD AGND
DRGND
AVDD
AGND
AVDD
AGND
T1-1T
T1
TIN1
SECPRI
J3
ANALOG
INPUT
CM
E30
CM
E3
COUT–
DA7
E18 E19
DB7
E25
E2
E5
DA3 DA5
T1–
T1+
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
44 43 42 41 40 39 38 37 36 35 34
12 13 14 16 17 18 19 20 21 22 15
DB6 DB5 DB4
DB3 DB2 DB1 DB0 DA0 DA1 DA2
DA4 DA6
DRVDD
GND
S1
PWDN
AVDD
GND
DRVDD
GND
AVDD
GND
AVDD
E13 E14
E1
GND
E15 E16
GND
GND
GND
AVDD
GND GND
AVDD
S3
CM
VAMP
U12
AD9481
P1
P2
P3
P4
1
2
3
4
P12
GND
VDL
GND
DRVDD
P1
P2
P3
P4
GND
VAMP
1
2
3
4
P1
GND
AVDD
GND
VCTRL
P13
P1
P2
P3
P4
1
2
3
4
AVDD
R3
100Ω
R2
100Ω
COUT+
GND
C16 X
GND
C20 X
TIN1
CM
GND
T1+
16 25 34
OPTIONAL TRANSFORMER
T2 ETC1-1-13
PRI SEC
CM T1–
R20 XX R30 XX
OP AMP CONFIGURATION REMOVE C3 REMOVE R29 AND R31
CLK+ CLK–
Q Q–
CLK
R26 82Ω
R27 50Ω
R24 510Ω
R23
510Ω
R16 130Ω
VCTRL
GND
GND
E6 E8
E9
E11
E10
AVDD
VCTRL
C4
0.1µF
GND
C11
0.1µF
J1
CLK CLKN
Q
R
VBB
VCC
VEE
Q
100LVEL16
2 3
7
1
4
8
5
6
U11
C2
0.1µF
C6
0.1µF
C5
0.1µF
R52 130Ω
VCTRL
GND
R25 82Ω
PADS FOR SHORTING EL16,
USED IF BYPASSING EL16
P15P14 P17P16
CLKN
CLK
Q– Q
GND
GND
R33
10kΩ
R55
X
R31
0Ω
R29
0Ω
R22
50Ω
C3
0.1µF
GND
AMPOUT E29
AMPOUT
E28
GND
C9
X
AMPIN
GND
GND
C10
0.1µF
GND
C8
X
R28 X R21 X
43 25 61
GND
C14 0.1µF
GND
C12 0.1µF
GND
C13
10µF
+
V+
TRIM/NC
U10
ADR510
1 2
3
V–
J4
DS–
GND
R1 50Ω
J2
DS+
C49
0.1µF
C48
0.1µF
GND
GND
E26 E27
GND
R35 50Ω
GND
R53 50Ω
05045-040
Figure 39. PCB Schematic (1 of 2)